On the Hardness of Approximating Stopping and Trapping Sets

McGregor, Andrew; Milenković, Olgica

doi:10.1109/tit.2010.2040941

Cited by 55 publications

(38 citation statements)

References 35 publications

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“…The lifted code in this case has length n = 990, and we are able to achieve the ACE spectrum (+∞, +∞, 17, 10,5). This improves the ACE spectrum of (+∞, +∞, 16, 9, 5) obtained in [10] for n = 1000.…”

Section: Numerical Resultsmentioning

confidence: 64%

“…A full characterization of dominant trapping sets over the AWGN channel, particularly for irregular codes, is not available. It is however known that enumerating such sets, in general, is a formidable task, see, e.g., [5]. Indirect measures of the error floor performance, which are computationally more efficient, have thus been used in the design and the analysis of the LDPC codes.…”

Section: Introductionmentioning

confidence: 99%

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Design of irregular quasi-cyclic protograph codes with low error floors

Asvadi

Banihashemi

Ahmadian-Attari

2011

2011 IEEE International Symposium on Information Theory Proceedings

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We propose a technique to design finite-length irregular low-density parity-check (LDPC) codes over the binaryinput additive white Gaussian noise (AWGN) channel with good performance in both the waterfall and the error floor region. The design process starts from a protograph which embodies a desirable degree distribution. This protograph is then lifted cyclically to a certain block length of interest. The lift is designed carefully to satisfy a certain approximate cycle extrinsic message degree (ACE) spectrum. The target ACE spectrum is one with extremal properties, implying a good error floor performance for the designed code. The proposed construction results in quasicyclic codes which are attractive in practice due to simple encoder and decoder implementation. Simulation results are provided to demonstrate the effectiveness of the proposed construction in comparison with similar existing constructions.

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Section: Numerical Resultsmentioning

confidence: 64%

Section: Introductionmentioning

confidence: 99%

Design of irregular quasi-cyclic protograph codes with low error floors

Asvadi

Banihashemi

Ahmadian-Attari

2011

2011 IEEE International Symposium on Information Theory Proceedings

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“…This dominant trapping set reduces the error floor performance of LDPC. By adding a line the following subset is identified as a graphical representation [7] So the trapping set identification and finding dominant trapping set by adding the line to the edges of check node with the lowest degree are shown. Figure (3.3a) shows that the degree of check node as two, and removing the lines from the subset graph will reduce the degrees as odd.…”

Section: Identifying Trapping Setmentioning

confidence: 99%

Progressive edge growth LDPC Encoder with spiral search algorithm

Anbalgan¹,

Kumar.P²

2017

IJET

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Trapping set causes the drop of performance in error floor region. Identification of TS is done by graphical method and enumerators. The lowest odd degree (minimal) TS is increasing the formation of more unsaturated nodes in iterative decoding. Progressive edge growth (PEG) Low-density parity check code (LDPC) [2] avoidance of trapping sets are mainly based on the distance and degree calculation of successive CN. This simple tool is used to eliminate TS when the encoder ensemble designs itself. Non-zero neighborhood search also made an influence on error floor. The spiral search method is used for Non-zero codeword search (NZCW) search for the first time in this research, at the decoder part. So, Non-zero codeword spiral search (NZCSS) converge fast with less number iteration, and this reduces the iteration of the decoder.

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“…This is the result of input that is decoded incorrectly due to the suboptimal decoding method. Predicting troublesome inputs and the nature of the error floor require long simulations (McGregor and Milenkovic 2010).…”

Section: Zaragoza 2006)mentioning

confidence: 99%

Optimization of multi-channel BCH error decoding for common cases

Dill¹,

Shrivastava²,

Oh³

2015

2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)

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Error correcting systems have put increasing demands on system designers, both due to increasing error correcting requirements and higher throughput targets. These requirements have led to greater silicon area, power consumption and have forced system designers to make trade-offs in Error Correcting Code (ECC) functionality. Solutions to increase the efficiency of ECC systems are very important to system designers and have become a heavily researched area.Many such systems incorporate the Bose-Chaudhuri-Hocquenghem (BCH) method of error correcting in a multi-channel configuration. BCH is a commonly used code because of its configurability, low storage overhead, and low decoding requirements when compared to other codes. Multi-channel configurations are popular with system designers because they offer a straightforward way to increase bandwidth. The ECC hardware is duplicated for each channel and the throughput increases linearly with the number of channels. The combination of these two technologies provides a configurable and high throughput ECC architecture.This research proposes a new method to optimize a BCH error correction decoder in multi-channel configurations. In this thesis, I examine how error frequency effects the utilization of BCH hardware. Rather than implement each decoder as a single pipeline of independent decoding stages, the channels are considered together and served by a pool of decoding stages. Modified hardware blocks for handling common cases are included and the pool is sized based on an acceptable, but negligible decrease in performance. i This thesis's experimental approach examines multi-channel configurations found in typical NAND flash systems. My experimental data shows that the proposed pooled group approach requires significantly fewer hardware blocks than a traditional multi-channel configuration. By allowing a 2% performance degradation and sizing the decoding pool appropriately, the scheme reduces hardware area by 47%-71% and dynamic power by 44%-59%.Additionally, I examined what improvements were possible with the improved design using the same hardware area as the traditional implementation. My experiments show that an improved throughput of 3x-5x can be achieved or NAND flash lifetime can be extended by 1.4x-4.5x. Dr. Shrivastava has provided invaluable input into both my research and my writing.

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On the Hardness of Approximating Stopping and Trapping Sets

Cited by 55 publications

References 35 publications

Design of irregular quasi-cyclic protograph codes with low error floors

Design of irregular quasi-cyclic protograph codes with low error floors

Progressive edge growth LDPC Encoder with spiral search algorithm

Optimization of multi-channel BCH error decoding for common cases

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