On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis

Riener, Heinz; Haaswijk, Winston; Mishchenko, Alan; Micheli, Giovanni De; Soeken, Mathias

doi:10.23919/date.2019.8715185

Cited by 37 publications

(17 citation statements)

References 16 publications

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“…More generally, SAT-based logic synthesis techniques are also used in rewriting algorithms. These algorithms optimize a network by replacing small subnetworks with their optimized versions obtained using a SAT-based exact synthesis approach [29], [30].…”

Section: B Bddsmentioning

confidence: 99%

Extending Boolean Methods for Scalable Logic Synthesis

et al. 2020

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Section: B Bddsmentioning

confidence: 99%

Extending Boolean Methods for Scalable Logic Synthesis

et al. 2020

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“…Full details for our DAG-aware replacement algorithm are outside the scope of this paper. We refer the interested reader to [11] and [12].…”

Section: Dag-awarenessmentioning

confidence: 99%

Scalable Generic Logic Synthesis

Riener

Testa

Haaswijk

et al. 2019

Proceedings of the 56th Annual Design Automation Conference 2019

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This paper proposes a novel methodology for multi-level logic synthesis that is independent from a specific graph data-structure, but formulates synthesis procedures using an abstract concept definition of a logic representation. The idea is to capture the essence of optimisations in a general manner and tailor only small performance-critical sections to the underlying logic representation. This generic, yet scalable approach, saves many man-months of development time and enables logic synthesis and technologymapping procedures parameterised in a logic representation. We present the generic design methodology and demonstrate its practicality by providing a complete state-of-the-art logic synthesis flow.

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“…Algebraic methods, as well as other local-search methods such as structural analysis and window simulation, are efficient but often sacrifice optimality. In contrast, Boolean methods, such as Boolean decomposition [3], resynthesis [4] and rewriting [5], usually achieve better quality at the cost of solving NP-hard Boolean problems using a binary decision diagram (BDD) [6], [7] package in earlier research, or a satisfiability (SAT) problem [8], [9] solver in more recent literature.…”

Section: Introductionmentioning

confidence: 99%

“…QUALITY ON XAGS COMPARING AGAINST ABC'S &M F S COMMAND.Inverter Graphs (XAGs). Table V compares the proposed framework with command &mfs[4] in ABC 5. The ifraigpreprocessed benchmarks are mapped into 2-LUT networks by the command &if -K 2 in ABC and read in as XAGs in mockturtle.…”

mentioning

confidence: 99%

A Simulation-Guided Paradigm for Logic Synthesis and Verification

Lee

Riener

Mishchenko

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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This paper proposes a new logic synthesis and verification paradigm based on circuit simulation. In this paradigm, high-quality, expressive simulation patterns are pre-generated to be reused in multiple runs of optimization and verification algorithms, resulting in reduced time-consuming Boolean computations such as SAT-solving. Methods to generate expressive simulation patterns are presented and compared, and a bitpacking technique to compress them is integrated into the implementation. The generated patterns are shown to be reusable across different algorithms and after network function modifications. A logic synthesis algorithm, Boolean resubstitution, and a verification algorithm, combinational equivalence checking, are two examples of using this paradigm. In simulation-guided Boolean resubstitution, simulation patterns are used for efficient filtering of optimization choices, leading to a lower cost in expanding the search space. By adopting the proposed paradigm, we achieve a 5.9% reduction in the number of AIG nodes, compared to 3.7% by a state-of-the-art resubstitution algorithm, within comparable runtime. In simulation-guided equivalence checking, the number of SAT solver calls is reduced by 9.5% with the use of the expressive simulation patterns accumulated in earlier logic synthesis stages.

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On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis

Cited by 37 publications

References 16 publications

Extending Boolean Methods for Scalable Logic Synthesis

Extending Boolean Methods for Scalable Logic Synthesis

Scalable Generic Logic Synthesis

A Simulation-Guided Paradigm for Logic Synthesis and Verification

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