On the distinction between triple gate (TG) and double gate (DG) SOI FinFETs: A proposal of critical top oxide thickness

Abstract

Distinction between triple gate (TG) and double gate (DG) silicon-on-insulator (SOI) FinFETs is presented here on the basis of their electrostatic and transport characteristics. A study missing in previous works on DG and TG FinFETs is the characterization of these structures with respect to the variation of top oxide thickness. In fact an exact value of the top-oxide thickness that can differentiate DG FinFETs from TG ones has not been reported yet. From this perspective, electrostatic and transport characteristics of DG and TG FinFETs having sub-10 nm fin dimensions are investigated in this work as a function of the top oxide thickness. To duly incorporate the quantummechanical (QM) effects in such nanoscale regime of operation, the devices are simulated by self-consistently solving the coupled Schrödinger's and Poisson's equations. Simulation results suggest that DG and TG FinFETs can be differentiated by a parameter which we define in our work with respect to the surface potentials existing beneath the top and side gates. This finding in effect proposes a critical top oxide thickness of FinFET that can draw the distinction between its DG and TG variants. The results also indicate that deposition of top oxide layer beyond a limit does not bring about any significant change in the electrostatic and transport characteristic of DG FinFETs in the ballistic limit.

III–V tri-gate quantum well MOSFET: Quantum ballistic simulation study for 10 nm technology and beyond

“…Raisul et. al presented a distinction between double gate (DG) and tri-gate (TG) FinFETs on the basis of electrostatic and transport analysis in terms of critical oxide thickness [36]. For SOI FinFETs, after a certain thickness of the top gate oxide the device 'on' current appears to be independent of top gate oxide thickness.…”