As CMOS technology scales down into the deep-submicron (DSM) domain, the costs of design and verification for Systems-On-Chip(SoCs) are rapidly increasing due to the inefficiency of traditional CAD tools. Relaxing the requirement of 100% correctness for devices and interconnects drastically reduces the costs of design but, at the same time, requires that SoCs be designed with some systemlevel fault-tolerance. In this paper, we introduce a new communication paradigm for SoCs, namely stochastic communication.
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