Observation of single event upsets in analog microcircuits

Koga, R.; Pinkerton, Steven D.; Moss, S. C.; Mayer, D.C.; LaLumondiere, Stephen; Hansel, S.J.; Crawford, K.B.; Crain, William R.

doi:10.1109/23.273472

Cited by 106 publications

(18 citation statements)

References 5 publications

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“…This model is supported by additional experiments in which an MBM10474A memory cell was exposed to a pulsed laser beam. (A description of the use of laser beams in SEU research can be found in [15].) Because the spot size of the laser beam is on the order of one micron, it was possible to expose one section of the cell at a time.…”

Section: Discussion: Seu Mechanismsmentioning

confidence: 99%

Ion induced charge collection and SEU sensitivity of emitter coupled logic (ECL) devices

Koga

Crain

Hansel

et al. 1995

IEEE Trans. Nucl. Sci.

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This paper presents single event upset (SEU) and latchup test results for selected Emitter Coupled Logic (ECL) microcircuits, including several types of low capacity SRAMs and other memory devices. The high speed of ECL memory devices makes them attractive for use in space applications. However, the emitter coupled transistor design increases susceptibility to radiation induced functional errors, especially SEU, because the transistors are not saturated, unlike the transistors in a CMOS device. Charge collection at the sensitive nodes in ECL memory elements differs accordingly. These differences are responsible, in part, for the heightened SEU vulnerability of ECL memory devices relative to their CMOS counterparts.Because the coupled transistors in an ECL memory cell remain in a non-saturated state continuously, the charge collection characteristics and SEU susceptibility of these devices differs from those fabricated in CMOS or TTL technology, For example, in ECL devices prompt charge collection at the sensitive nodes appears to be more important than drift charge collection in causing upset.In the following, we present SEU and latchup results relevant to the use of ECL devices in space, and discuss the implications of these findings for our current understanding of upset mechanisms in this famiry of devices. p "cc .

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Section: Discussion: Seu Mechanismsmentioning

confidence: 99%

Ion induced charge collection and SEU sensitivity of emitter coupled logic (ECL) devices

Koga

Crain

Hansel

et al. 1995

IEEE Trans. Nucl. Sci.

Self Cite

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“…Under some test conditions, the increase exceeded two orders of magnitude compared to normal incidence. Negligible change in device performance was noted after an integrated 63 MeV proton fluence of over 4.8x10 11 cm -2 .…”

Section: ) Lasermate Ttc-155m2 and Ttc-155m4mentioning

confidence: 99%

“…The cross sections and LET th s for the comparators are only slightly sensitive to the applied bias. However, the LM139 cross section and LET th has a strong dependence on the input differential voltage, first reported in [11]. The HS139 has an LET threshold of approximately 8-10 and a cross section of 3x10 -4 cm 2 .…”

Section: ) Harris Hs139 and National Semiconductor Lm139mentioning

confidence: 99%

Recent radiation damage and single event effect results for microelectronics

O'Bryan

LaBel

Reed

et al.

1999 IEEE Radiation Effects Data Workshop. Workshop Record. Held in Conjunction With IEEE Nuclear and Space Radiation Effects C

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“…Such events are most often caused by a large area of photo-generated charge following the impact of a high mass ion [24]; from an ion strike at grazing angle affecting multiple memory cells [25]; from byproducts of a nuclear spallation having occurred in overlaying materials [26]; or from strikes on the memory control circuitry that result in the corruption of an entire word line [27].…”

Section: B Ecc Model Assumptionsmentioning

confidence: 99%

Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs

Bajura

Boulghassoul

Naseer

et al. 2007

IEEE Trans. Nucl. Sci.

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Abstract-A mathematical bit error rate (BER) model for upsets in memories protected by error-correcting codes (ECCs) and scrubbing is derived. This model is compared with expected upset rates for sub-100-nm SRAM memories in space environments. Because sub-100-nm SRAM memory cells can be upset by a critical charge ( crit ) of 1.1 fC or less, they may exhibit significantly higher upset rates than those reported in earlier technologies. Because of this, single-bit-correcting ECCs may become impractical due to memory scrubbing rate limitations. The overhead needed for protecting memories with a triple-bit-correcting ECC is examined relative to an approximate 2X "process generation" scaling penalty in area, speed, and power.

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Observation of single event upsets in analog microcircuits

Cited by 106 publications

References 5 publications

Ion induced charge collection and SEU sensitivity of emitter coupled logic (ECL) devices

Ion induced charge collection and SEU sensitivity of emitter coupled logic (ECL) devices

Recent radiation damage and single event effect results for microelectronics

Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs

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