Numerical modeling of PLL jitter and the impact of its non-white spectrum on the SNR of sampled signals

Dait, N. Da; Harteneck, M.; Sandner, C.; Wiesbauer, A.

doi:10.1109/ssmsd.2001.914934

Cited by 7 publications

(5 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Where j (n) is a stochastic process whose power spectral density (PSD) is not necessarily white. In fact, a clock signal generated by a PLL usually has low-pass jitter [25]. We assume j (n) has a variance σ 2 j and a zero mean, such that T s represents the effective clock period.…”

Section: A Jittered Lpsc-dacmentioning

confidence: 99%

Low-Pass Filtering SC-DAC for Reduced Jitter and Slewing Requirements on CTSDMs

Vercaemer

Raman

Rombouts

2019

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

In this paper, a technique is introduced that improves the performance of one-bit continuous-time sigma delta modulators (CTSDMs) using a low-pass filtering switched capacitor digital to analog converter (LPSC-DAC). This DAC effectively combines an infinite impulse response filter with a switched capacitor resistor DAC (SCR-DAC). The resulting DAC is inherently immune toward inter-symbol interference. Moreover, by filtering the feedback signal in the discrete-time domain, the jitter robustness of the modulator is greatly improved and most importantly the slewing requirements on the OpAmps in the modulator's loop filter are greatly relaxed up to a level that the OpAmps can be scaled down toward their ultimate noise limited power level. Furthermore, this LPSC-DAC does not suffer from the SCR-DAC's disadvantageous trade-off between the modulator's jitter, slewing, and anti-aliasing performance. We also show how to compensate for the extra pole of the LPSC-DAC, such that the CTSDM's loop filter, noise-and signal-transfer function remains unchanged. As a result, this technique is completely transparent to the system level designer and established system-level design techniques for sigma delta modulators remain applicable.

show abstract

Section: A Jittered Lpsc-dacmentioning

confidence: 99%

Low-Pass Filtering SC-DAC for Reduced Jitter and Slewing Requirements on CTSDMs

Vercaemer

Raman

Rombouts

2019

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

show abstract

“…In the literature, such as in [7,8,10], it is assumed that timing jitter can be modelled with a Gaussian distribution. However, with a finite number of samples, the distribution of timing jitter has not only a white noise component, but also a doubly integrated white noise component (1/f 2 ) [11,12]. It is also shown that the SINRs of charge sampling and voltage sampling are almost equivalent when the jitter is sufficiently small.…”

Section: Intoductionmentioning

confidence: 99%

“…4. There are two major noise sources [11]. One is the voltage-controlled oscillator (VCO) and the other one is the temperaturecompensated crystal oscillator (TCXO) [12].…”

Section: Pll Modelmentioning

confidence: 99%

See 1 more Smart Citation

Influence of timing jitter on quadrature charge sampling

2007

View full text Add to dashboard Cite

The influence of timing jitter on quadrature charge sampling for a direct conversion receiver has been evaluated. In contrast to voltage sampling, the charge sampling mixer integrates the signal current instead of tracking the signal voltage. The charge sampling mixer has been applied to RF direct sampling in wireless receivers. The influence of timing jitter on charge sampling has been analysed in some literatures. However, in wireless receivers, quadrature sampling is required in order to demodulate I-phase and Q-phase signals. Different from charge sampling, timing jitter causes crosstalk between these signals. The influence of timing jitter on quadrature sampling is investigated.

show abstract

“…Because the key idea here is to demonstrate the accuracy of the presented analysis, for simplicity, the jitter for both the transmitter and receiver is assumed to be white Gaussian noise. We refer the interested readers to [21] and [22] for a more detailed model of PLL generated jitter.…”

Section: Behavioral Simulationsmentioning

confidence: 99%

Analysis of PLL clock jitter in high-speed serial links

Hanumolu¹,

Casper²,

Mooney³

et al. 2003

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

We analyze the effects of transmitter and receiver phased-locked loop (PLL) phase noise, which translates to time-domain clock/data jitter, on the performance of high-speed transceivers. Analytical expressions are derived to incorporate both transmitter and receiver clock jitter into serial link operation. A method to calculate the worst-case noise margin degradation due to clock jitter is discussed in order to obviate impractical time-domain simulations. This analysis relies on the assumption that the channel is linear and time-invariant and, hence, can be characterized by an impulse response. A simple extension to equalized serial links is also presented. The analysis is verified through behavioral simulations using a realistic/measured channel model.

show abstract

Numerical modeling of PLL jitter and the impact of its non-white spectrum on the SNR of sampled signals

Cited by 7 publications

References 1 publication

Low-Pass Filtering SC-DAC for Reduced Jitter and Slewing Requirements on CTSDMs

Low-Pass Filtering SC-DAC for Reduced Jitter and Slewing Requirements on CTSDMs

Influence of timing jitter on quadrature charge sampling

Analysis of PLL clock jitter in high-speed serial links

Contact Info

Product

Resources

About