Non-arithmetic carry chains for reconfigurable fabrics

Frederick, M.T.; Somani, Arun K.

doi:10.1109/iccd.2007.4601892

Cited by 4 publications

(9 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The results presented in this work are indicative of LEs which can operate in both (K-1) and K-LUT modes, as depicted in Fig. 2, and supported by the Stratix and [5]. The ChainMap algorithm can be adapted to support pure carry-select, (K-1)-LUT chains, by searching for a (K-1)-feasible cut when d = t, and a K-feasible cut when d = t.…”

Section: Contributions and Implicationssupporting

confidence: 69%

“…1(b). A modified carry-select architecture presented in [5] operates in either mode depicted in Fig. 2, and forms heterogeneous chains as in Fig.…”

Section: Chains In Fpgasmentioning

confidence: 99%

“…Chains are an underutilized, low latency resource waiting to be exploited. This work presents a polynomial time, depth optimal logic chain technology mapping solution, applicable to the Stratix K-LUT chain and the Kwidth chain reuse cell presented in [5], and easily adapted to standard (K-1) carry-select chains. The motivation is to create generic logic chains not limited to arithmetic operations.…”

Section: Chains In Fpgasmentioning

confidence: 99%

See 2 more Smart Citations

Beyond the arithmetic constraint

Frederick

Somani

2008

Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays

Self Cite

View full text Add to dashboard Cite

Look-up table based FPGAs have migrated from a niche technology for design prototyping to a valuable end-product component and, in some cases, a replacement for general purpose processors and ASICs alike. One way architects have bridged the performance gap between FPGAs and ASICs is through the inclusion of specialized components such as multipliers, RAM modules, and microcontrollers. Another dedicated structure that has become standard in reconfigurable fabrics is the arithmetic carry chain. Currently, it is only used to map arithmetic operations as identified by HDL macros. For non-arithmetic operations, it is an idle but potentially powerful resource.This work presents ChainMap, a polynomial-time delayoptimal technology mapping algorithm for the creation of generic logic chains in LUT-based FPGAs. ChainMap requires no HDL macros be preserved through the design flow. It creates logic chains, both arithmetic and non-arithmetic, in an arbitrary Boolean network whenever depth increasing nodes are encountered. Use of the chain is not reserved for arithmetic, but rather any set of gates exhibiting similar characteristics. By using the carry chain as a generic, near zero-delay adjacent cell interconnection structure an average optimal speedup of 1.4x is revealed, and an average relaxed speedup of 1.25x can be realized simultaneously with a 0.95x LUT utilization decrease.

show abstract

Section: Contributions and Implicationssupporting

confidence: 69%

“…1(b). A modified carry-select architecture presented in [5] operates in either mode depicted in Fig. 2, and forms heterogeneous chains as in Fig.…”

Section: Chains In Fpgasmentioning

confidence: 99%

Section: Chains In Fpgasmentioning

confidence: 99%

See 1 more Smart Citation

Beyond the arithmetic constraint

Frederick

Somani

2008

Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays

Self Cite

View full text Add to dashboard Cite

show abstract

“…Similar to our work, one recent paper has presented a nonarithmetic carry chain in which two 2-LUTs are combined to form a 3-LUT [15]; however, it was based on a carryselect structure used in Altera's Stratix, which has since been deprecated. Starting with the Stratix II, Altera's carry chains have employed a ripple-carry structure.…”

Section: Related Workmentioning

confidence: 83%

Reducing the pressure on routing resources of FPGAs with generic logic chains

Parandeh-Afshar

Zgheib

Brisk

et al. 2011

Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays

View full text Add to dashboard Cite

Routing resources in modern FPGAs use 50% of the silicon real estate and are significant contributors to critical path delay and power consumption; the situation gets worse with each successive process generation, as transistors scale more effectively than wires. To cope with these challenges, FPGA architects have divided wires into local and global categories and introduced fast dedicated carry chains between adjacent logic cells, which reduce routing resource usage for certain arithmetic circuits (primarily adders and subtractors).Inspired by the carry chains, we generalize the idea to connect lookup tables (LUTs) in adjacent logic cells. By exploiting the fracturable structure of LUTs in current FPGA generations, we increase the utilization of the existing LUTs in the logic cell by providing new inputs along the logic chain, but without increasing the I/O bandwidth from the programmable interconnect. This allows us to increase the logic density of the configurable logic cells while reducing demand for routing resources, as long as the mapping tools are able to exploit the logic chains. Our experiments using the combinational MCNC benchmarks and comparing against an Altera Stratix-III FPGA show that the introduction of logic chains reduce the average usage of local routing wires by 37%, with a 12% reduction in total wiring (local and global); this translates to improvements in dynamic power consumption of 18% in the routing network and 10% overall, while utilizing 4% fewer logic cells, on average.

show abstract

“…The latter merely requires the selective propagation of the carry input or its replacement by a local computation but never needs to produce the inverted carry. Although the benefits of such increased functional flexibility were already described in the 1990s [9] and later re-affirmed by Frederick and Somani themselves [10], it is, in fact, not available on any major commercial FPGA device family but on Altera's retired Stratix family. This deficiency, for instance, precludes the implementation of a chained wide XOR operation.…”

Section: A Generalized Carry-chain Usagementioning

confidence: 94%

Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains

Preußer

Spallek

2010

2010 International Conference on Field Programmable Logic and Applications

View full text Add to dashboard Cite

This paper presents an approach to the automatic mapping of arbitrary combinational circuits to the arithmetic carry-chain structures widely available in modern FPGAs. This capability is highly valuable as it enables the utilization of these fast special-purpose structures for general-purpose logic. The described approach is both automatic and generally applicable to all carry-chain architectures designed for binary addition. It, thus, lifts severe constraints left by previous works. It helps to reduce the pressure on the general-purpose routing resources and accelerates critical logic paths. The proposed mapping is further shown to enhance the logic capability of a logic block containing a k-input lookup table (k-LUT) to implement many (k + 1)-input functions on common FPGA architectures. This, in particular, also applies to all logic functions with a noninverting path as introduced by Anderson and Wang [1]. This makes their envisioned gains in logic density achievable even on current devices without requiring their architectural extension. The benefits of the carry-chain mapping are experimentally evaluated on the basis of combinational MCNC benchmarks. It is shown how carry chains can be recovered within a functional standard mapping and that a device mapping aware of carry chains achieves a reduction of the combinational delay of about a 20 percent.

show abstract

Non-arithmetic carry chains for reconfigurable fabrics

Cited by 4 publications

References 2 publications

Beyond the arithmetic constraint

Beyond the arithmetic constraint

Reducing the pressure on routing resources of FPGAs with generic logic chains

Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains

Contact Info

Product

Resources

About