NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures

Prodromou, Andreas; Panteli, Andreas; Nicopoulos, Chrysostomos; Sazeides, Yiannakis

doi:10.1109/micro.2012.15

Cited by 78 publications

(52 citation statements)

References 39 publications

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“…Similar number for NoCAlert [14] was 97%, and the technique reached 100% after 28 cycles. The respective numbers for ForEVeR [13] were 30% and 11950 cycles.…”

Section: Resultsmentioning

confidence: 58%

A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers

Saltarelli

Niazmand

Raik

et al. 2015

2015 Euromicro Conference on Digital System Design

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This paper proposes a framework for automated evaluation of concurrent online checkers. The novelty of the underlying approach lies in its completeness (i.e. ability of formally proving the presence or absence of true misses), minimal fault detection latency and accurate, fully automated evaluation of the fault detection characteristics of the checkers. The methodology consists of creating a pseudo-combinational version of the circuit under test, specifying the environment in terms of valid input stimuli and providing the assertions for generating the checkers, which will thereafter be evaluated by the framework. In this paper, a case-study on the control part (routing and arbitration) of a Network-on-Chip (NoC) router has been carried out. It shows on a realistic application that the framework is capable of accurately and formally evaluating the quality of individual concurrent checkers which constitutes an important task in fault tolerant system design. The case study shows that the proposed approach helps achieving high fault coverage in a single clock-cycle.

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“…Similar number for NoCAlert [14] was 97%, and the technique reached 100% after 28 cycles. The respective numbers for ForEVeR [13] were 30% and 11950 cycles.…”

Section: Resultsmentioning

confidence: 58%

A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers

Saltarelli

Niazmand

Raik

et al. 2015

2015 Euromicro Conference on Digital System Design

View full text Add to dashboard Cite

show abstract

“…Moreover, the authors in [20] propose NoCAlert, an online fault detection mechanism which is based on the idea of invariance checking. Through the invariance checking, the outputs of the control logic modules of the NoC are checked for wrong outputs based on the current inputs (microchecker models in hardware).…”

Section: Fault Detection In Nocs Relatedmentioning

confidence: 99%

A Design Space Exploration Framework for ANN-Based Fault Detection in Hardware Systems

Savva

Theocharides

Nicopoulos

2017

Journal of Electrical and Computer Engineering

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This work presents a design exploration framework for developing a high level Artificial Neural Network (ANN) for fault detection in hardware systems. ANNs can be used for fault detection purposes since they have excellent characteristics such as generalization capability, robustness, and fault tolerance. Designing an ANN in order to be used for fault detection purposes includes different parameters. Through this work, those parameters are presented and analyzed based on simulations. Moreover, after the development of the ANN, in order to evaluate it, a case study scenario based on Networks on Chip is used for detection of interrouter link faults. Simulation results with various synthetic traffic models show that the proposed work can detect up to 96-99% of interrouter link faults with a delay less than 60 cycles. Added to this, the size of the ANN is kept relatively small and they can be implemented in hardware easily. Synthesis results indicate an estimated amount of 0.0523 mW power consumption per neuron for the implemented ANN when computing a complete cycle.

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“…The field is set when its corresponding link detects a fault. Detection of faults can be done by implementing BIST (Built-In System Test) [14], [31]; however, fault detection is beyond the scope Figure 7(a). The LC and FC are split into 4 independent blocks corresponding to each direction (+x, -x, etc.).…”

Section: Link and Fault Controllersmentioning

confidence: 99%

“…Built-In Self Tests (BISTs) are commonly used to detect errors in systems. Recently, NoCAlert [14] was proposed which detected faults in real-time with 0% false negatives. Low overhead checkers were used to detect faults without the need of periodic or triggered-based testing.…”

Section: Related Workmentioning

confidence: 99%

QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers

DiTomaso

Kodi

Louri

2014

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)

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Network-on-Chips (NoCs) are quickly becoming the standard communication paradigm for the growing number of cores on the chip. While NoCs can deliver sufficient bandwidth and enhance scalability, NoCs suffer from high power consumption due to the router microarchitecture and communication channels that facilitate inter-core communication. As technology keeps scaling down in the nanometer regime, unpredictable device behavior due to aging, infant mortality, design defects, soft errors, aggressive design, and process-voltage-temperature variations, will increase and will result in a significant increase in faults (both permanent and transient) and hardware failures. In this paper, we propose QORE -a fault tolerant NoC architecture with Quad-Function Channel (QFC) buffers. The use of QFC buffers and their associated control (link and fault controllers) enhance fault-tolerance by allowing the NoC to dynamically adapt to faults at the link level and reverse propagation direction to avoid faulty links. Additionally, QFC buffers reduce router power and improve performance by eliminating in-router buffering. Our simulation results using real benchmarks and synthetic traffic mixes show that QORE improves speedup by 1.3× and throughput by 2.3× when compared to state-of-the art fault tolerant NoCs designs such as Ariadne and Vicis. Moreover, using Synopsys Design Compiler, we also show that network power in QORE is reduced by 21% with minimal control overhead.

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NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures

Cited by 78 publications

References 39 publications

A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers

A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers

A Design Space Exploration Framework for ANN-Based Fault Detection in Hardware Systems

QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers

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