An FPGA implementation of a multilayer perceptron neural network is presented. The system is parameterized both in network related aspects (e.g.: number of layers and number of neurons in each layer) and implementation parameters (e.g.: word width, pre-scaling factors and number of available multipliers). This allows to use the design for different network realizations, or to try different areaspeed trade-offs simply by recompiling the design. Fixed point arithmetic with pre-scaling configurable in a per laye…
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