Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008
DOI: 10.1145/1366110.1366121
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NBTI-aware flip-flop characterization and design

Abstract: With the scaling down of the CMOS technologies, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the corresponding reduction in the long-term reliability of CMOS circuits. This paper investigates the effect of NBTI phenomenon on the setup and hold times of flip-flops. First, it is shown that NBTI tightens the setup and hold timing constraints imposed on the flip-flops in the design. Second, different types of flip-flops exhibit diffe… Show more

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Cited by 30 publications
(19 citation statements)
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“…The raising electric field through the oxide thickness generates interface traps in P-type devices and results in unwanted increase in threshold voltage (Vth) [23] which ultimately affects propagation delay and noise margins. In [5] and [18], investigations have been done on propagation delay for various flip-flops subject to NBTI aging.…”
Section: Background and Related Workmentioning
confidence: 99%
“…The raising electric field through the oxide thickness generates interface traps in P-type devices and results in unwanted increase in threshold voltage (Vth) [23] which ultimately affects propagation delay and noise margins. In [5] and [18], investigations have been done on propagation delay for various flip-flops subject to NBTI aging.…”
Section: Background and Related Workmentioning
confidence: 99%
“…These points are the critical points which can be defined by the designer. There can be two or three points as mentioned in [8]; for example, the points with minimum setup or hold times.…”
Section: Critical Pair Definition On Csht Contourmentioning
confidence: 99%
“…In [7], the effect of NBTI on different low power and high performance flip-flops was studied; however, no solution was offered to alleviate the problem. The authors of [8] introduced an ad-hoc selective transistor-level sizing to combat the NBTI effect without considering energy consumption as part of the objective.…”
Section: Introductionmentioning
confidence: 99%
“…Different types of flipflops exhibit different levels of susceptibility to NBTI-induced change in their setup/hold time values. An elaborated NBTI-aware transistor sizing technique can minimize the NBTI effect on timing characteristics of the flip-flops [Abrishami et al 2008]. Furthermore, memory-like structures have a special characteristic in NBTI degradation.…”
Section: Nbti and Nbti-aware Designmentioning
confidence: 99%