NBTI-aware data allocation strategies for scratchpad memory based embedded systems

Abstract

While performance and power continue to be important metrics for embedded systems, as CMOS technologies continue to shrink, new metrics such as variability and reliability have emerged as limiting factors in the design of modern embedded systems. In particular, the reliability impact of pMOS negative bias temperature instability (NBTI) has become a serious concern. Recent works have shown how conventional leakage optimization techniques can help mitigate NBTI-induced aging effects on cache memories. In this paper we focus specifically on scratchpad memory (SPM) and present novel software approaches as a means of alleviating the NBTI-induced aging effects. In particular, we demonstrate how intelligent software directed data allocation strategies can extend the lifetime of partitioned SPMs by means of distributing the idleness across the memory sub-banks.

SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic

“…This results in drive current reduction and noise increase, which in turn causes a degradation of the device delay. The threshold variation is estimated to be 5-15% per year [4], [5] depending on the targeted technology and its environment, while the path delay degradation follows the same trend, though with a smaller magnitude. NBTI's effect on the longterm stability of functional logic expresses itself through the incapability of storing a correct value at memory elements such as flip-flops due to the de-synchronization between clock distribution and signal propagation through the logic paths of a circuit.…”

Gate-level modelling of NBTI-induced delays under process variations

“…Among them, [6] proposed an approach in order to alleviate the NBTI-induced aging effects in Static Random Access Memories (SRAMs). Another approach, [11], uses an experimentally verified NBTI model to study DC noise margins in conventional 6T SRAM cells as a function of NBTI degradation in the presence of PVs.…”

“…The variation of V THp of pMOS transistors due to dynamic NBTI (i.e. when the stress and recovery phases are iterating) is estimated to be 5-15% per year depending on the targeted technology and its environment [6] [7]. The threshold voltage shift for devices at static NBTI (i.e.…”

Investigating the use of an on-chip sensor to monitor NBTI effect in SRAM

“…For this set of simulations, it was considered the SRAM cell to be aged by a factor of 7.5% per year, i.e., the threshold of the two pFET transistors of the cell shifted at a rate of 7.5% per year, according to the fault model assumed and described in Section II. This value was selected by considering literature works that suggest typical � V thp hanging from 5 to 15% per year [5]. As can be seen in this figure, as old is the memory cell lesser is its capability to discharge the virtual V DD' node during a write operation because of the reduced current drive capability of the pFET transistors that have their threshold voltage increased.…”

“…Previous works found in the literature have addressed the NBTl problem. Among them, [5] proposed an approach as a means of alleviating the NBTl-induced aging effects. In particular, they demonstrate how intelligent software directed data allocation strategies can extend the lifetime of partitioned scratchpad memories by means of distributing the idleness across memory sub-banks.…”