Nanoscale tri gate MOSFET for Ultra low power applications using high-k dielectrics

Nirmal, D.; Kumar, Pratap; Joy, Doreen; Jebalin, Binola K.; Kumar, Neeraj

doi:10.1109/inec.2013.6465939

Cited by 14 publications

(6 citation statements)

References 17 publications

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“…where λ is the feature length and can be obtained after applying boundary conditions given in equations [3][4][5] :…”

Section: Analytical Modelmentioning

confidence: 99%

“…2 The reduction in device size minimizes the gate control on region, causes several problems like short channel effects (SCE's) and hot carrier effects (HCE's). [3][4][5] For reduction of SCE's multi-gate FET structures such as Double Gate Fin-FET, Triple Gate Fin-FET and surrounding gate MOSFET (SG MOSFET) were proposed. 6 A nonlinear Fin-FET model is also implemented for emerging FinFET technology for non-quasi statics (NQS) effects.…”

Section: Introductionmentioning

confidence: 99%

“…This ineffectiveness had been taken care by small size MOSFET, where SiO 2 layer has been grown as a gate dielectric on semiconductor substrate as it provides better electrical insulation 2 . The reduction in device size minimizes the gate control on region, causes several problems like short channel effects (SCE's) and hot carrier effects (HCE's) 3–5 . For reduction of SCE's multi‐gate FET structures such as Double Gate Fin‐FET, Triple Gate Fin‐FET and surrounding gate MOSFET (SG MOSFET) were proposed 6 .…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

SiC‐based analytical model for gate‐stack dual metal nanowireFETwith enhanced analog performance

Neeraj

Goel

Sharma

et al. 2022

Int J Numerical Modelling

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In this paper, silicon carbide-based analytical model for gate-stack dual metal nanowire field effect transistor (gate-stack DM NW FET) has been analyzed by solving the 2D Poisson's equation using parabolic approximation method for electric potential, subthreshold current and subthreshold slope. The results have been examined for various silicon carbide film depth and channel length. The results predicted by the analytical model have excellent agreement with simulated results obtained by ATLAS 3D device simulator. A gate-stack having high k-dielectric material, that is, Hafnium oxide (HfO 2 ) along with aluminum oxide (Al 2 O 3 ) has been used. Also, performance characteristics of gate-stack DM NW FET have been compared with the performance characteristics of nanowire field effect transistor (NW FET), Nanowire field effect transistor (NW FET) (Sic) and dual metal nanowire field effect transistor (DM NW FET) (SiC). It is so proved that our proposed device, that is, gate-stack DM NW FET (4H-SiC) exhibits superior performance in terms of drain current (I ds) , transconductance (g m ), output conductance (g d ) and cut off frequency (f T ) than the existing devices.

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“…where λ is the feature length and can be obtained after applying boundary conditions given in equations [3][4][5] :…”

Section: Analytical Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

SiC‐based analytical model for gate‐stack dual metal nanowireFETwith enhanced analog performance

Neeraj

Goel

Sharma

et al. 2022

Int J Numerical Modelling

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“…Feasible nitridation treatment process is a good choice for stacked high-k/metal gate (HK/MG) in deep-nano node process manufacturing to reduce the amount of oxygen vacancy [1] in HK dielectric deposition. Therefore the gate leakage will be possibly retarded and the reliability performance enhanced.…”

Section: Introductionmentioning

confidence: 99%

GIDL and gated-diode metrologies for 28nm HK/MG nMOSFETs in nitridation annealing temperatures

Wang

Chen

Lee

et al. 2014

2014 International Symposium on Next-Generation Electronics (ISNE)

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GIDL and gated diode tests are useful to probe the integrity of surface channel. In this work, the latter seems better to the former in detecting the trapping/detraaping on the channel surface. As V G~ -0.62V, the peak effect of drain current was observed for gate diode test, but not apparent for GIDL test for all of tested devices even though the gate bias was swept back and forth at the accumulation mode of nMOSFETs. The decoupled plasma nitridation treatment for HK dielectric with both annealing temperatures shows the trap amount with the higher annealing is less than that with the lower one at the middle vertical field operation, but the whole drain leakage with the lower annealing is better than that with the higher one as V G =-Vcc due to the high possibility to form the micro-or nano-crystallization causing the huge PooleFrenkel tunneling.

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“…The advantages are not only to freely adjust the threshold voltage (V T ), but to reduce the power consumption or delay time because of the lower gate resistance in the circuit concern. Using a feasible HK gate dielectric [6]- [8] material incorporating the manufacturing line and optimizing the device performance is an interesting task.…”

Section: Introductionmentioning

confidence: 99%

Gate Leakage Characteristics for 28 nm HfZrO<sub><italic>x</italic></sub> pMOSFETs After DPN Process Treatment With Different Nitrogen Concentration

Lee

Wang

et al. 2014

IEEE Trans. Plasma Sci.

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Feasibly adjusting the gate leakage and the device performance in balance is an obvious challenge. Additionally, stacking the high-k dielectric as a gate dielectric in nanonode process is an appreciate way to promote the drive current in pMOSFETs. Unfortunately, the amount of oxygen vacancy or the interfacial layer thickness on the surface channel will possibly reduce the drive current owing to the increasing magnitude of threshold voltage and increase in the gate leakage degrading the standby capability in circuit operation. To retard this disadvantage or intensify the device quality, applying a lower pressure decoupled-plasma nitridation process to obliquely reform the amount of oxygen vacancy is a feasible alternative. On the basis of tested data, the nitridation treatment in a higher N 2 concentration is better than that in a lower one, such as the improvement of gate leakage, drive current, subthreshold swing, and channel mobility in pMOSFETs, especially for shorter channel-length devices.Index Terms-Decoupled-plasma nitridation (DPN), gate dielectric, gate leakage, high-k dielectric.

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Nanoscale tri gate MOSFET for Ultra low power applications using high-k dielectrics

Cited by 14 publications

References 17 publications

SiC‐based analytical model for gate‐stack dual metal nanowireFETwith enhanced analog performance

SiC‐based analytical model for gate‐stack dual metal nanowireFETwith enhanced analog performance

GIDL and gated-diode metrologies for 28nm HK/MG nMOSFETs in nitridation annealing temperatures

Gate Leakage Characteristics for 28 nm HfZrO<sub><italic>x</italic></sub> pMOSFETs After DPN Process Treatment With Different Nitrogen Concentration

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