Superlattices and Microstructures volume 39, issue 5, P395-405 2006 DOI: 10.1016/j.spmi.2005.08.020 View full text
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Ali A. Orouji, M. Jagadesh Kumar

Abstract: Abstract-Design considerations for a below 100 nm channel length SOI MOSFET with electrically induced shallow source/drain junctions are presented. Our simulation results demonstrate that the application of induced source/drain extensions to the SOI MOSFET will successfully control the SCEs and improve the breakdown voltage even for channel lengths less than 50 nm. We conclude that if the side gate length equals the main gate length, the hot electron effect diminishes optimally.