N-port strictly non-blocking optical router based on Mach-Zehnder optical switch for photonic networks-on-chip

IEICE Electron. Express

et al. 2019

Optical networks on chip (ONoC) delivers a promising alternative to meet growing needs of higher bandwidth and low power consumption in manycore processors. Optical routers are the key element in ONoCs that significantly affect the performance of overall network. In this letter, we propose a rearrangeable non-blocking 6 × 6 router (RoR) constructed with 2 × 2 hybrid photonic-plasmonic switching (HPPS) elements. Router architectures with 15 HPPS elements and an optimized design using reduced HPPS elements are presented and analyzed. In optimized form, proposed design consumes only 12 HPPS elements which results in low insertion loss and crosstalk noise in comparison to the unoptimized architecture. We observe up to 50% reduction in switching elements count in comparison to other router architecture of same radix.

Section: Comparisons Of Optical Routersmentioning

confidence: 91%

Section: Introductionmentioning

confidence: 99%

RoR: A low insertion loss design of rearrangeable hybrid photonic-plasmonic 6 × 6 non-blocking router for ONoCs

IEICE Electron. Express

et al. 2019

“…From Table 10, it can be observed that optical switches (OS) constructed using proposed framework has advantage of reduced number of OSUs and per path maximum number of OSUs. For the scale of 4 × 4, proposed optimized OS utilizes only 5 OSUs which is lesser than [15], [24] and [29] and similar to proposed in [14]. In addition, proposed optimized 4 × 4 OS uses lesser number of per path OSUs i.e.…”

Section: A Hardware Cost Of Non-blocking Switch Topologiesmentioning

confidence: 94%

“…Higher port count of optical switches for high end application in future on-chip optical interconnects and large bandwidth communication applications are greatly anticipated [21]- [24]. For instance, high performance computers (HPC) require optical switching fabrics that can evade the limitations of power consumption and port count caused due to conventional interconnects [25].…”

Section: Introductionmentioning

confidence: 99%

An Algorithmic Framework to Construct Optical Switch via Scaling From N-to-2N Ports for Optical Network on Chip

et al. 2019

IEEE Access

Optical network-on-chip (ONoC), designed with non-blocking optical switches, is gaining a significant research attention to meet the upcoming requirements of higher throughput, larger bandwidth, lower latency, and reduced power consumption for manycore processors. In this paper, we propose an algorithmic framework to construct non-blocking optical switches with multiple interconnection possibilities. The design is accomplished by scaling the optical switch from N-to-2N ports using two intermediate mapping matrices each of size 2N × 2N. These mapping matrices are the row and column permutations of identity matrices, where 1's represent passive interconnections among the optical switching units (OSUs). The proposed framework provides validation to the design by identifying all the non-blocking permutations of the mapping matrices, thereby, providing a flexibility to adopt any permutation as an interconnection scheme. Furthermore, it has the ability to quantify the redundancy in switching combinations which exists for any input-to-output routing, authenticates the non-blocking feature of the optical switch and to reduce the number of optical switching units while preserving the non-blocking characteristic. For the scaled 4 × 4 and 6 × 6 optical switches, we respectively identified 16 and 192 different interconnections to build multiple non-blocking switches. Moreover, a 20% reduction in OSUs is achieved by optimizing a 6 × 6 switch. The influence of the insertion loss, power consumption, and crosstalk noise on various scaled optical switch networks are also analyzed and compared with several existing optical switch topologies. INDEX TERMS Optical network-on-chip (ONoC), optical switch, optimization, scalability, silicon nanophotonics. The associate editor coordinating the review of this manuscript and approving it for publication was Sukhdev Roy. network increases, OSU count also increases which leads to higher latency, poor power consumption and insertion loss [5]. Scalability of high radix optical switch, designed for high performance applications, requires special design considerations to alleviate the intrinsic characteristics of insertion loss, crosstalk noise and power consumption in optical onchip interconnects. Increase in switching units also affects the complexity and footprint of optical switch [6]. Optimal number of OSUs and their configuration can reduce overall crosstalk noise, insertion loss and power consumption for the optical switch [7]. Several non-blocking architectures based on different network topologies have been proposed in literature

“…Designing optical switch architecture with an optimum number of OSE can minimize overall insertion loss and power consumption in the network topology [21]. Numerous methodologies have been proposed to construct optical switch/router topologies with optimal arrangements of OSEs and different methods have been proposed to optimize the number of OSEs to improve overall network performance [22][23][24][25][26]. In this regard, several multi-stage blocking, strictly non-blocking (SNB), and rearrangeable non-blocking (RNB) optical switch architectures have been presented [27,28], e.g., Benes [29], Spanke-Benes [30], cross switch matrix [31] and Path Independent Loss (PILOSS) [32].…”

Section: Introductionmentioning

confidence: 99%

HoneyComb ROS: A 6 × 6 Non-Blocking Optical Switch with Optimized Reconfiguration for ONoCs

et al. 2019

Electronics

Silicon photonics has become a commonly used paradigm for on-chip interconnects to meet the requirements of higher bandwidth in computationally intensive applications for manycore processors. Design of an optical switch is a vital aspect while constructing an optical NoC topology which influences the performance of network. We present a HoneyComb optimized reconfigurable optical switch (HCROS), a 6 × 6 non-blocking optical switch where optimized reconfiguration of optical links utilizing the states of basic 2 × 2 optical switching elements (OSE) was achieved while keeping the input-output (I/O) interconnection intact. The proposed 6-port HCROS architecture was further optimized to reduce the number of OSEs to minimize overall power consumption. We proposed a generic algorithm to find the optimal switching combination of OSEs for a particular I/O link to minimize the insertion loss and power consumption. In comparison to other non-blocking architectures, a maximum of 66% reduction in OSEs was observed for the optimized HCROS, which consumes only 12 OSEs. Simulations were performed for all 720 I/O links in different configurations to evaluate the power consumption and insertion loss. We observed up to 92% power savings in the case of optimized HCROS as compared to un-optimized HCROS, and a 79% minimization in insertion loss was also reported as a result of optimization.