MuSiC An Event-Flow Computer for Fast Simulation of Digital Systems

Hahn, Winfried; Fischer, Kristian

doi:10.1109/dac.1985.1585963

Cited by 13 publications

(2 citation statements)

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“…The parameter H reflects this reduction in t E and is defined as H ----tE B/tEs (13) Two interesting bounds can he derived from (11) by simplifying (10) for the evaluation-time-dominant and communication-time-dominate cases and substituting (10) and (12) into (11). When the event/function evaluation time dominates all other time components in the specialpurpose machine (tEVAL>>tCoM,tSYNC) and the processor load is balanced (/3=1), the speed-up becomes …”

Section: Speed-upmentioning

confidence: 99%

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Performance analysis and design of a logic simulation machine

Wong

Franklin

1987

Proceedings of the 14th Annual International Symposium on Computer Architecture - ISCA '87

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The high costs associated with logic simulation of large VLSI circuits has led to the need for new computer architectures tailored to the simulation task. Such architectures have the potential for significant speed-ups over software-based logic simulators executing on standard sequential computers. This paper presents a model of one class of multiprocessor simulation architectures and compares the performance of some of these machines using data obtained from simulations of VLSI circuits. In addition, we discuss the implications of our results on machine design and examine the sensitivity of the model to variations in circuit characteristics.

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Section: Speed-upmentioning

confidence: 99%

“…The techniques employed in achieving these speed-ups vary from microcode implementation of simulation algorithms to the development of specialpurpose multiprocessors tailored to the simulation algorithm. Theoretical studies of possible simulation architectures have also been undertaken [9][10][11].…”

Section: Introductionmentioning

confidence: 99%