Multilevel circuit partitioning

Alpert, Charles J.; Huang, Jen-Hsin; Kahng, Andrew B.

doi:10.1145/266021.266275

Cited by 165 publications

(186 citation statements)

References 38 publications

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“…The survey by Alpert and Kahng [10] provides a detailed description and comparison of various such schemes. Recently a new class of hypergraph bisection algorithms has been developed [11,23,15,22], that are based upon the multilevel paradigm. In these algorithms, a sequence of successively smaller (coarser) hypergraphs is constructed.…”

Section: Introductionmentioning

confidence: 99%

“…This bisection is then successively projected to the next level ®ner hypergraph, and at each level an iterative re®ne-ment algorithm (e.g., KL [1] or FM [3]) is used to further improve the bisection. Experiments presented in [23,15,22] have shown that multilevel hypergraph bisection algorithms can produce substantially better partitionings than those produced by non-multilevel schemes. In particular, hMETIS [20], a multilevel hypergraph bisection algorithm based upon the work in [23] has been shown to ®nd substantially better bisections than current state-of-the-art iterative re®nement algorithms for the ISPD98 benchmark set that contains many large circuits [18].…”

Section: Introductionmentioning

confidence: 99%

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Multilevel k-way hypergraph partitioning

Karypis

Kumar

Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361)

230

272

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In this paper, we present a new multilevel k-way hypergraph partitioning algorithm that substantially outperforms the existing state-of-the-art K-PMaLR algorithm for multiway partitioning, both for optimizing local as well as global objectives. Experiments on the ISPD98 benchmark suite show that the partitionings produced by our scheme are on the average 15% to 23% better than those produced by the K-PMaLR algorithm, both in terms of the hyperedge cut as well as the (K À 1) metric. Furthermore, our algorithm is signi®cantly faster, requiring 4 to 5 times less time than that required by K-PMaLR.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Multilevel k-way hypergraph partitioning

Karypis

Kumar

Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361)

230

272

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“…MB*-tree is inspired by the success of the multilevel framework in graph/circuit partitioning such as Chaco [10], hMetis [12], and ML [2], placement such as MPL [4], £ This work was partially supported by the National Science Council of Taiwan by Grant No. NSC-91-2215-E-002-038.…”

Section: Introductionmentioning

confidence: 99%

Multilevel floorplanning/placement for large-scale modules using B*-trees

Lee¹,

Chang

Hsu

et al. 2003

Proceedings of the 40th Annual Design Automation Conference

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We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-scale building modules. The MB*-tree adopts a two-stage technique, clustering followed by declustering. The clustering stage iteratively groups a set of modules based on a cost metric guided by area utilization and module connectivity, and at the same time establishes the geometric relations for the newly clustered modules by constructing a corresponding B*-tree for them. The declustering stage iteratively ungroups a set of the previously clustered modules (i.e., perform tree expansion) and then refines the floorplanning/placement solution by using a simulated annealing scheme. In particular, the MB*-tree preserves the geometric relations among modules during declustering, which makes the MB*-tree an ideal data structure for the multilevel floorplanning/placement framework. Experimental results show that the MB*-tree obtains significantly better silicon area and wirelength than previous works. Further, unlike previous works, MB*-tree scales very well as the circuit size increases.

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“…We also note that both PROP and SHRINK-PROP are "flat" partitioners, i.e., they do not use the multilevel paradigm use in many recent partitioners like hMetis [22], ML [3], and LSR/MFFS [8]. The multilevel paradigm is orthogonal to our techniques, and can be used with both PROP and SHRINK-PROP to yield faster and probably better results.…”

Section: B Ispd-98 Benchmarksmentioning

confidence: 99%

A probability-based approach to VLSI circuit partitioning

Dutt¹,

Deng²

33rd Design Automation Conference Proceedings, 1996

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Abstract-Iterative-improvement two-way min-cut partitioning is an important phase in most circuit placement tools, and finds use in many other computer-aided design (CAD) applications. Most iterative improvement techniques for circuit netlists like the Fiduccia-Mattheyses (FM) method compute the gains of nodes using local netlist information that is only concerned with the immediate improvement in the cutset. This can lead to misleading gain information. Krishnamurthy suggested a lookahead (LA) gain calculation method to ameliorate this situation; however, as we show, it leaves room for improvement. We present here a probabilistic gain computation approach called probabilistic partitioner (PROP) that is capable of capturing the future implications of moving a node at the current time. We also propose an extended algorithm SHRINK-PROP that increases the probability of removing recently "perturbed" nets (nets whose nodes have been moved for the first time) from the cutset. Experimental results on medium-to large-size ACM/SIGDA benchmark circuits show that PROP and SHRINK-PROP outperform previous iterative-improvement methods like FM (by about 30% and 37%, respectively) and LA (by about 27% and 34%, respectively). Both PROP and SHRINK-PROP also obtain much better cutsizes than many recent state-of-the-art partitioners like EIG1, WINDOW, MELO, PARABOLI, GFM and GMetis (by 4.5% to 67%). Our empirical timing results reveal that PROP is appreciably faster than most recent techniques. We also obtain results on the more recent ISPD-98 benchmark suite that show similar substantial mincut improvements by PROP and SHRINK-PROP over FM (24% and 31%, respectively). It is also noteworthy that SHRINK-PROP's results are within 2.5% of those obtained by hMetis, one of the best multilevel partitioners. However, the multilevel paradigm is orthogonal to SHRINK-PROP. Further, since it is a "flat" partitioner, it has advantages over hMetis in partition-driven placement applications.Index Terms-Clustering effect, iterative-improvement, min-cut partitioning, probabilistic gain, VLSI circuit.

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Multilevel circuit partitioning

Cited by 165 publications

References 38 publications

Multilevel k-way hypergraph partitioning

Multilevel k-way hypergraph partitioning

Multilevel floorplanning/placement for large-scale modules using B*-trees

A probability-based approach to VLSI circuit partitioning

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