Multi-objective mapping for mesh-based NoC architectures

Abstract

In this paper we present an approach to multi-objective exploration of the mapping space of a mesh-based network-on-chip architecture. Based on evolutionary computing techniques, the approach is an efficient and accurate way to obtain the Pareto mappings that optimize performance and power consumption. Integration of the approach in an exploration framework with a kernel based on an event-driven trace-based simulator makes it possible to take account of important dynamic effects that have a great impact on mapping. Validation on both synthesized traffic and real applications (an MPEG-2 encoder/decoder system) confirms the efficiency, accuracy and scalability of the approach.

Multi-objective mapping optimization via problem decomposition for many-core systems

“…The fitness values of f , uc and ul (2) in this case, should be speculated at this sub-problem. Without an actual mapping configuration, we can still calculate a bound that a fitness value can possibly be in.…”

“…EDA optimization problems are typically defined by multiple objectives that have to be optimized simultaneously [2], [19], [24]. Therefore, solutions may not be comparable with each other, some being better in some of the objectives and worse in others.…”

“…For instance, L p norm of processor utilization in state s is uc s (s) = L p ({uc cs (c, s)|∀c ∈ C}) and the weighted sum of all states is uc = s∈S w s · uc s (s). ul (2) and ul (3) can be calculated in a similar way. In summary, the objective vector f to be minimized is f = (uc, ul (2) , ul (3) ).…”

“…ul (2) and ul (3) can be calculated in a similar way. In summary, the objective vector f to be minimized is f = (uc, ul (2) , ul (3) ).…”

“…As the processor list c cl should always be kept as sorted, the heap sorting is used here. ul (2),min can be calculated in a similar way. Likewise, the maximum values, uc max can also be estimated considering the worst-case mapping.…”