Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching

Grannaes, Marius; Jahre, Magnus; Natvig, Lasse

doi:10.1007/978-3-642-11515-8_19

Cited by 10 publications

References 10 publications

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“…Despite progress in designing prefetchers, many misses are left uncovered. Figure 3 shows the simulated coverage and accuracy of numerous state-of-the-art academic prefetchers [11]- [13], [16]- [18], [21], [30], [38], [39]. As a matter of fact, in the best-case scenarios, prefetchers can eliminate up to 50% of LLC misses, meaning many accesses still access slow main memory.…”

Section: Motivation and Backgroundmentioning

confidence: 99%

“…Coverage is the fraction of misses eliminated by prefetching, and accuracy is the fraction of useful prefetches. In the best cases (e.g., DCPT [13]), 40% of misses are eliminated but with high overhead of 40% inaccuracy. High inaccuracy of prefetchers makes level prediction very challenging.…”

Section: Ratiomentioning

confidence: 99%

“…Prefetchers somewhat mitigate the latency impact of levelby-level lookup by moving data between levels prior to the execution of load instructions [11]- [13], [16]- [18], [21], [30], [38], [39]. Although prefetchers improve system performance, many loads are still exposed to sequential-lookup delays.…”

Section: Introductionmentioning

confidence: 99%

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Reducing Load Latency with Cache Level Prediction

Majid¹,

Mattan²

2021

Preprint

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High load latency that results from deep cache hierarchies and relatively slow main memory is an important limiter of single-thread performance. Data prefetch helps reduce this latency by fetching data up the hierarchy before it is requested by load instructions. However, data prefetching has shown to be imperfect in many situations. We propose cachelevel prediction to complement prefetchers. Our method predicts which memory hierarchy level a load will access allowing the memory loads to start earlier, and thereby saves many cycles. The predictor provides high prediction accuracy at the cost of just one cycle added latency to L1 misses. Experimental results show speedup of 7.8% on generic, graph, and HPC applications over a baseline with aggressive prefetchers.

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Section: Motivation and Backgroundmentioning

confidence: 99%

Section: Ratiomentioning

confidence: 99%

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Reducing Load Latency with Cache Level Prediction

Majid¹,

Mattan²

2021

Preprint

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“…More advanced schemes like Stride Directed Prefetching avoids needless prefetches when the processor's referencing pattern strides through nonconsecutive memory blocks [5]. Further prediction enhancements include use of Reference Prediction Tables [2], Global History Buffers [18], and Delta Correlation Prediction Tables [9] to dynamically update stride distances based on encountered cache misses. The overhead, both in large history tables as well as time and energy consuming data transfers due to misprediction, makes precomputation attractive for relevant applications.…”

Section: :5mentioning

confidence: 99%

Runtime Precomputation of Data-Dependent Parameters in Embedded Systems

Hammari

Kjeldsberg

Catthoor

2018

ACM Trans. Embed. Comput. Syst.

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In many modern embedded systems the available resources, e.g., CPU clock cycles, memory and energy, are consumed non-uniformly while the system is under exploitation. Typically, the resource requirements in the system change with different input data that the system process. This data trigger different parts of the embedded software resulting in different operations executed that require different hardware platform resources to be used. A significant research effort has been dedicated to develop mechanisms for run-time resource management, e.g. branch prediction for pipelined processors, prefetching of data from main memory to cache, and scenario based design methodologies. All these techniques rely on the availability of information at run-time about the upcoming changes in the resource requirements. In this paper we propose a method for detection of upcoming resource changes based on preliminary calculation of software variables that have the most dynamic impact on the resource requirements in the system. We apply the method on a modified real-life biomedical algorithm with real input data and estimate a 40% energy reduction as compared to static DVFS scheduling. Comparing to dynamic dvfs scheduling, an 18% energy reduction is demonstrated. CCS Concepts: • Computer systems organization → Embedded systems; Firmware; Real-time systems; • Hardware → On-chip resource management;

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“…The top three prefetchers submitted to the First Data Prefetching Championship (DPC-1) [7], titled AMPM (Access Map Pattern Matching), GHB-LDB (Global History Buffer -Local Delta Buffer), and PDFCM (Prefetching base on a Differential Finite Context Machine), utilized significantly more sophisticated and novel approaches to the prefetching problem.…”

Section: Related Workmentioning

confidence: 99%

An Approach to Data Prefetching Using 2-Dimensional Selection Criteria

Jean¹,

Sebastian²,

Andrew³

et al. 2015

Preprint

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We propose an approach to data memory prefetching which augments the standard prefetch buffer with selection criteria based on performance and usage pattern of a given instruction. This approach is built on top of a pattern matching based prefetcher, specifically one which can choose between a stream, a stride, or a stream followed by a stride. We track the most recently called instructions to make a decision on the quantity of data to prefetch next. The decision is based on the frequency with which these instructions are called and the hit/miss rate of the prefetcher. In our approach, we separate the amount of data to prefetch into three categories: a high degree, a standard degree and a low degree. We ran tests on different values for the high prefetch degree, standard prefetch degree and low prefetch degree to determine that the most optimal combination was 1, 4, 8 lines respectively. The 2 dimensional selection criteria improved the performance of the prefetcher by up to 9.5% over the first data prefetching championship winner. Unfortunately performance also fell by as much as 14%, but remained similar on average across all of the benchmarks we tested.

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Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching

Cited by 10 publications

References 10 publications

Reducing Load Latency with Cache Level Prediction

Reducing Load Latency with Cache Level Prediction

Runtime Precomputation of Data-Dependent Parameters in Embedded Systems

An Approach to Data Prefetching Using 2-Dimensional Selection Criteria

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