Multi-corner, energy-delay optimized, NBTI-aware flip-flop design

Abstract

With the CMOS transistors being scaled to sub 45nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the corresponding reduction in the long-term reliability of CMOS circuits. This paper investigates the effect of NBTI phenomenon on the setup and hold times of flip-flops. First, it is shown that NBTI tightens the setup and hold timing constraints imposed on the flip-flops in the design. Second, an efficient algorithm is introduced for characterizing the codependent setup and hold time (CSHT) contours. Third, we introduce a multicorner optimization problem to minimize the energy-delay product of the flip-flops. The optimization relies on mathematical programming to find the best transistor sizes. Finally, we apply our proposed optimization formulation on True Single-Phase Clock (TSPC) flip-flops and show the simulation results.

Selective Flip-Flop Optimization for Circuit Reliability

“…Since the optimized flip-flop will replace the corresponding flip-flop in the design, the delay degradation is compared to the fresh delay of the original flip-flop in order to give a better understanding of how close the aged delay of the optimized flip-flop is to the fresh delay of the original design. Basically, scenario 1 is similar to the methods proposed in many flip-flop optimization methods such as [1,13] in the sense that they consider a multiplication of energy and delay (e.g., the PDP or the Energy Delay Product (EDP)) as the optimization target. Scenario 1 is able to effectively reduce the PDP by increasing the delay and reducing the leakage, but this may result in an unacceptable timing for S-BTI corners.…”

“…Therefore, the total power in of flip-flops under S-BTI is determined by the leakage power. Even though scenario 2's design is much better for flip-flops which are only under the aging impact compared to the original and the state-of-the-art [1] flipflop designs, the impact of 10% voltage-drop is significant on the delay, i.e. 49% delay degradation.…”

“…Various methods have been proposed to address the impact of aging and voltagedrop on flip-flops [1,13,23,25]. For example, [1] proposes a method to improve flip-flop reliability for a set of corners with different working conditions such as temperatures and voltages by altering the sizing of transistors. These studies mostly optimize flip-flops for dynamic BTI stress condition, and flip-flops under static BTI are mostly overlooked.…”

Design automation and synthesis techniques for approximate computing

“…In this Section the Flip Flop VOS characterization component of VOSsim is used to explore the flip flop's operation and behavior when the voltage supply is decreased as well as when timing violations occur. The flip flop setup and hold times depend on the supply voltage, however the setup time is more sensitive to it and the hold time at nominal voltage is reasonably pessimistic [93,95].…”