2015 IEEE International Electron Devices Meeting (IEDM) 2015
DOI: 10.1109/iedm.2015.7409607
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Cited by 45 publications
(28 citation statements)
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“…Many cycles of integration and OPC will be spend where the choice of design architecture becomes extremely important for long-term manufacturing cost vs. fast yield ramp and time to market. The reduction of all parasitic resistances and capacitances in the contact to Mx area will appear as the most innovation for technologies below 14 and IOnm to gain in further SoC scaling maintaining its performance level [7,8].…”
Section: Future Cmos Technology Scalingmentioning
confidence: 99%
“…Many cycles of integration and OPC will be spend where the choice of design architecture becomes extremely important for long-term manufacturing cost vs. fast yield ramp and time to market. The reduction of all parasitic resistances and capacitances in the contact to Mx area will appear as the most innovation for technologies below 14 and IOnm to gain in further SoC scaling maintaining its performance level [7,8].…”
Section: Future Cmos Technology Scalingmentioning
confidence: 99%
“…The small contact CD dramatically gives rise to the contact resistance (Re, in Q), making Re a dominant parasitic factor for the modern CMOS technology [2]. Therefore, in the 7nm/5nm technology node, ultralow contact resistivity (pe, in Q'cm 2 ) below 2x 10-9 Q'cm 2 is required to ensure high transistor performance [3].…”
Section: Introductionmentioning
confidence: 99%
“…Moore's law scaling requires that the contact size scales at ~0.5× from node to node [2]. This requires that target ߩ values should be below 6, 4, and 2 n-cm 2 for 22 nm, 14 nm and 10 nm technology nodes, respectively.…”
Section: Introductionmentioning
confidence: 99%