1979
DOI: 10.1109/isscc.1979.1155930
View full text
|
|
Share

Abstract: THIS PAPER will describe a monolithic analog multiplier/divider circuit which achieves nonlinearity error of less than 0.03%, with large signal bandwidth in excess of 3MHz. The circuit design makes use of a on-chip nonlinearity cancellation technique which is capable of cancelling virtually all nonlinearity caused by the emitter resistance of the core transistors. The monolithic chip also includes three high-speed differential input amplifiers which are used t o set three input currents 11.12, and 14.The mono…

expand abstract