GaN HEMT and MOS monolithic integration on silicon substratesCross section schematic of integrated devices 1 Introduction Gallium nitride HEMT devices are ideal for high-power operation due to their high mobility and large breakdown voltage as a result of the large bandgap of the material (3.4 eV) [1]. Currently, the applications for AlGaN/GaN HEMT devices are limited to RF and microwave power transistors, as well as some preliminary power switching applications, due to the restrictive cost of growth compared to silicon-based alternatives. The development of growth on silicon substrates allows for a cheaper alternative than the current norm of silicon carbide substrates [2,3].The growth of AlGaN/GaN on Si also opens the path to the integration of high-density, low-power MOS logic with high power HEMTs, expanding the number of applications for which GaN can be competitive. Applications that can take advantage of this could include highpower switching circuits that use MOS logic for control, or chemical/biological sensors which can take advantage the chemical inertness of the AlGaN/GaN material structure for detection, combined with low-power MOS read-out circuitry.This work reports on the monolithic integration of AlGaN/GaN HEMTS and MOS technology on silicon <111> substrates using a windowed epitaxy technique. A co-integration process which first includes the hightemperature MOS processing steps, followed by the GaN device formation is presented. Improved measured MOS and HFET IV characteristics compared to those previously reported are presented [4]. Integration of Si MOS and AlGaN/GaN HEMT devices has also been reported by Chung et al.[5] using a wafer bonding technique. This allows for the use of <100> oriented substrates, currently preferred for MOS devices.2 Substrate preparation and growth The windowed growth process on silicon <111> substrates presented in [6] is used to prepare wafers with dedicated regions for MOS and GaN devices. This technique uses a silicon dioxide layer to protect regions of the silicon wafer for MOS processing during GaN epitaxy. This layer is subsequently lifted off using a HF wet etch after growth, The GaN heterostructure is grown by ammonia-MBE between 780• C and 900• C with a NH 3 flow of 200 sccm. The layer stack, which is shown in Fig. 1, uses the stress relief strategy developed in [2] in order to overcome the lattice and thermal expansion mismatch between GaN and silicon. It should be noted that the sample used in this work has an unintentionally doped buffer layer rather than using carbon doping. The growth results in mobility of 917 cm 2 /Vs, a sheet resistance of 445 Ω/sq and a sheet carrier concentration of 1.07x1013 cm −2 . Additionally, this sample is able to withstand long thermal cycles at temperatures greater than 950• C when passivated with a thin oxide capping layer. Previous growths have shown some decomposition of the material under these conditions.3 Device processing The limited thermal budget of the MOS process is the most challenging requirement of the co-i...