Module assignment and interconnect sharing in register-transfer synthesis of pipelined data paths

Park, N.; Kurdahi, Fadi

doi:10.1109/iccad.1989.76895

Cited by 23 publications

(8 citation statements)

References 3 publications

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“…Previous efforts in data-path synthesis used models that can be divided into two major types: In the first type, a register and multiplexer bus transaction model is derived for the particular communications of the designs [5][10] [11] [12]. This model is typically represented as a connection graph and conventional graph search and matching techniques are applied.…”

Section: Previous Workmentioning

confidence: 99%

Symbolic Modeling and Evaluation of Data Paths

Monahan

1995

32nd Design Automation Conference

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Section: Previous Workmentioning

confidence: 99%

Symbolic Modeling and Evaluation of Data Paths

Monahan

1995

32nd Design Automation Conference

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“…Fan-outs of the buses from each multiplier is kept low and each of these buses once instantiated can be reused for the four data transfers without any multiplexing overhead. A similar idea to reduce interconnections during assignment for pipelined datapaths is given in [4] where the authors consider assignment of paths (not E-templates) and…”

Section: Using E-templates In Synthesismentioning

confidence: 97%

“…Recently, as research showed that the interconnect has a first order effect on the quality of the overall design [21, there has been a growing interest in interconnect optimization. Several high-level synthesis systems have incorporated interconnect minimization as one of the primary goals [3,4]. However, none of these have targeted power reduction -they reduce the number of buses but ignore the cost of accessing them.…”

Section: 2 Related Workmentioning

confidence: 99%

Exploiting regularity for low-power design

Mehra¹,

Rabaey²

Proceedings of International Conference on Computer Aided Design

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Current day behavioral-synthesis techniques produce architectures that are power-inefficient in the interconnect. Experiments have demonstrated that in synthesized designs, about 10 to 40% of the total power may be dissipated in buses, multiplexors, and drivers. We present a novel approach targeted at the reduction of power dissipation in interconnect elements-buses, multiplexors, and buffers. The scheduling, assignment, and allocation techniques presented in this paper exploit the regularity and c o m n computational patterns in the algorithm to reduce the fan-outs and fan-ins of the interconnect wires, resulting in reduced bus capacitances and a simplified interconnect structure. Average power savings of 47% and 49% in buses and multiplexors, respectively, are demonstrated on a set of benchmark examples.

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“…Within the PICO system, width clustering is used to bind operations of narrow bitwidth to common resources to reduce datapath cost [20]. Assignment of scheduled operations to resources with the goal of increasing interconnect sharing has been proposed [24]. The advantage of preprocessing heuristics is that they are fast and usually achieve good results when used in conjunction with a traditional scheduling algorithm.…”

Section: Related Workmentioning

confidence: 99%

Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System

Fan¹,

Kudlur

Park

et al.

38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05)

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Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware synthesis system where the schedule is used to determine various components of the hardware, including datapath, storage, and interconnect, the goals of a scheduler change drastically. In addition to achieving the traditional goals, the scheduler must proactively make decisions to ensure efficient hardware is produced. This paper proposes two exact solutions for cost sensitive modulo scheduling, one based on an integer linear programming formulation and another based on branch-and-bound search. To achieve reasonable compilation times, decomposition techniques to break down the complex scheduling problem into phase ordered sub-problems are proposed. The decomposition techniques work either by partitioning the dataflow graph into smaller subgraphs and optimally scheduling the subgraphs, or by splitting the scheduling problem into two phases, time slot and resource assignment. The effectiveness of cost sensitive modulo scheduling in minimizing the costs of function units, register structures, and interconnection wires are evaluated within a fully automatic synthesis system for loop accelerators. The cost sensitive modulo scheduler increases the efficiency of the resulting hardware significantly compared to both traditional cost unaware and greedy cost aware modulo schedulers. Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05) 0-7695-2440-0/05 $20.00 © 2005 IEEE Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05) 0-7695-2440-0/05 $20.00 © 2005 IEEE

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Module assignment and interconnect sharing in register-transfer synthesis of pipelined data paths

Cited by 23 publications

References 3 publications

Symbolic Modeling and Evaluation of Data Paths

Symbolic Modeling and Evaluation of Data Paths

Exploiting regularity for low-power design

Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System

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