Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs

Straka, Martin; Kastil, Jan; Kotásek, Zdenĕk

doi:10.1109/ddecs.2010.5491793

Cited by 17 publications

(8 citation statements)

References 9 publications

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“…The idea of identifying run-time errors in COTS FPGAs is investigated in [4][5] [6]. In these papers the authors describe an on-line checker to identify errors in different applications embedded in FPGAs.…”

Section: Related Workmentioning

confidence: 99%

Non-intrusive fault tolerance in soft processors through circuit duplication

Ferlini

Silva

Bezerra

et al. 2012

2012 13th Latin American Test Workshop (LATW)

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The flexibility introduced by Conunercial-Off-The Shelf (COTS) SRAM based FPGAs in on-board system designs make them an attractive option for military and aerospace applications. However, the advances towards the nanometer technology come together with a higher vulnerability of integrated circuits to radiation perturbations. In mission critical applications it is important to improve the reliability of applications by using fault-tolerance techniques. In this work, a non-intrusive fault tolerance technique has been developed. The proposed technique targets soft processors (e.g. LEON3), and its detection mechanism uses a Bus Monitor to compare output data of a main soft-processor with its redundant module. In case of a mismatch, an error signal is activated, triggering the proposed fault tolerance strategy. This approach shows to be more efficient than the state-of-the-art Triple Modular Redundancy (TMR) and Software Implemented Hardware Fault Tolerance (SIHFT) approaches in order to detect and to correct faults on the fly with low area overhead and with no major performance penalties. The chosen case study is an under development On Board Computer (OBC) system, conceived to be employed in future missions of the Brazilian Institute of Space Research (INPE).

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Section: Related Workmentioning

confidence: 99%

Non-intrusive fault tolerance in soft processors through circuit duplication

Ferlini

Silva

Bezerra

et al. 2012

2012 13th Latin American Test Workshop (LATW)

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“…Duplex systems with various types of Concurent Error Detection (CED) technique are popular FT architecture for SEU mitigation in SRAM-based FPGA [8]. As examples, CED techniques, on-line checkers or dual-rail logic can be mentioned.…”

Section: Introductionmentioning

confidence: 99%

Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA

Kastil

Straka

Mičulka

et al. 2012

2012 15th Euromicro Conference on Digital System Design

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In this paper, a dependability analysis of fault tolerant systems implemented into the SRAM-based FPGA is presented. The fault tolerant architectures are based on the redundancy of functional units associated with a concurrent error detection technique which uses the principles of partial dynamic reconfiguration as a recovery mechanism from a fault occurrence. Architectures are tested by injecting soft errors into partial bitstream in FPGA by an SEU injector and the faults coverage of this architecture is obtained. From faults coverage, the failure rate and repair rate are evaluated. Then, for fault tolerant architecture Markov dependability models are created and how the reliability and availability parameters derived from this model for different configurations of architectures and faulty modules is demonstrated. The reliability analysis results are then shown.

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“…It is shown that the diverse design improves reliability for randomly introduced faults. Three modern fault tolerant architectures based on DPR and TMR or duplex with on-line checkers as a type of Concurrent Error Detection technique are proposed in [9]. Redundancy functional units are implemented in the dynamic part of the design and replaced if an upset strikes one or more of them.…”

Section: Introductionmentioning

confidence: 99%

A run time adaptive architecture to trade-off performance for fault tolerance applied to a DVB on-board processor

Veljković

Riesgo

Torre

et al. 2014

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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Reliability is one of the key issues in space applications. Although highly flexible and generally less expensive than predominantly used ASICs, SRAM-based FPGAs are very susceptible to radiation effects. Hence, various fault tolerant techniques have to be applied in order to handle faults and protect the design. This paper presents a reconfigurable onboard processor capable of run-time adaptation to harsh environmental conditions and different functional demands. Run-time reconfigurability is achieved applying two different reconfiguration methodologies. We propose a novel selfreconfigurable architecture able to on demand duplicate or triplicate part of the design in order to form DMR and TMR structures. Moreover, we introduce two different approaches for voting the correct output. The first one is a traditional voter that adapts to different DMR/TMR domain positions whereas the second implies comparing the captured flip-flop values directly from the configuration memory read through ICAP. The comparison is done periodically by an embedded processor thus completely excluding the voting mechanism in hardware. The proposed run-time reconfiguration methodology provides savings in terms of device utilization, reconfiguration time, power consumption and significant reductions in the amount of radhard memory used by partial configurations.

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Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs

Cited by 17 publications

References 9 publications

Non-intrusive fault tolerance in soft processors through circuit duplication

Non-intrusive fault tolerance in soft processors through circuit duplication

Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA

A run time adaptive architecture to trade-off performance for fault tolerance applied to a DVB on-board processor

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