Modeling and Optimization of Chip Cooling with Two-Phase Vapor Chambers

A Learning-Based Thermal Simulation Framework for Emerging Two-Phase Cooling Technologies

“…2 (a). We divide the whole chip into grids as in prior work [17]. For the processing layer, the grid cell structure is shown in Fig.…”

“…In this way, we do not need to model the heat sink on top of the VC. Instead, we use a previously established relationship between HTC and thermal resistance to define R hybrid [13], [17]. In addition, we assume the VC itself only contains saturated vapor at a constant temperature [8], [15].…”

“…Two-phase cooling thermal models are usually designed by calculating the temperaturedependent heat transfer coefficient 1 (HTC) [8], [12], [14], [15]. In these models, pre-computed temperature-dependent HTC correlations embedded in the simulation framework are functions of temperature and cooling parameters (e.g., coolant type, flow velocity, saturation temperature, and structural parameter such as microchannel width and height, micropillar height, diameter, and pitch [12], [15], [17]). The HTC correlations are derived either based on in-house prototypes or using computational fluid dynamics (CFD) modules in COMSOL and ANSYS [1], [15].…”

“…The reason for this accuracy loss is that these correlations are derived from various prototypes with different microchannel height, width, shape, and mass flow velocity values, and they are not sufficiently modular for application to any other microchannel structures and flow velocities. Yuan et al introduced a CTM for two-phase VCs with micropillar wick evaporators [17], [18]. The HTC values of micropillar wick geometries are extracted from a finite element model and stored in a lookup table.…”

Neural network-based cooling design for high-performance processors

“…The cooling performance and cooling power of these potential solutions vary significantly based on the cooling parameters (such as liquid flow velocity, evaporator design, TEC current, etc.) ( Yuan et al., 2019a ; 2019b ). The selection of the cooling technologies and the cooling parameters also needs to consider the chip architecture, chip size, and floorplan, as well as the power profiles of the applications running on the given chip.…”