Mixed-Crossing-Avoided Escape Routing of Mixed-Pattern Signals on Staggered-Pin-Array PCBs

Wang, Kan; Dong, Sheqin; Hua-xi, Wang; Chen, Qian; Lin, Tao

doi:10.1109/tcad.2014.2301676

Cited by 10 publications

(2 citation statements)

References 8 publications

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“…Li et al [22] employed a two-stage scheme and a minimum-cost maximum-flow algorithm to simultaneously route all differential pairs. Wang and Jiao et al [23], [24] developed unordered and ordered escape routing algorithms for staggered pin arrays, taking into consideration the constraints of differential pairs.…”

Section: A Escape Routing and Region Routingmentioning

confidence: 99%

Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB Routing

Yin,

Jin,

Chen

et al. 2023

IEEE Access

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In recent years, there has been extensive research on the routing problem of printed circuit boards (PCBs). Due to the increasing number of pins, high pin density, and unique physical constraints, manual PCB routing has become a time-consuming task to achieve design convergence. Previous work decomposed the problem into escape routing and area routing, focusing on these problems separately. However, there was always a gap between these two problems, requiring significant human effort for iterative algorithm adjustments. Furthermore, previous area routing work mainly focused on routing between ball grid array (BGA) packages in escape routing. However, in practice, many components are not in the form of BGA packages, such as passive devices, decoupling capacitors, and through-hole pin arrays. Therefore, it is necessary to study a unified routing approach. The current unified routing approach adopts the A* algorithm, but there is still room for improvement in routing speed. This paper proposes a new algorithm called Unet-Astar, which accelerates the routing efficiency by employing deep learning algorithms in a simulated environment. Additionally, a Deeper Unet is proposed for generating recommended regions for the routing algorithm. The new network structure can provide more contextual information, thereby improving routing efficiency. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm. Specifically, for all given test cases, our router achieves approximately a 70% improvement in runtime speed compared to the old router. Another major contribution of this work is the development of a routing problem set generator, which can generate parameterized routing problem sets with different sizes and constraints. This enables the evaluation of different routing algorithms and the generation of training datasets for future data-driven routing methods. All the code has been open-sourced and can be found at https://github.com/Firesuiry/Unet-Astar-For-PCB-Routing. INDEX TERMS physical design, printed circuit board, routing, Machine learning I. INTRODUCTION 1 This article has been accepted for publication in IEEE Access.

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Section: A Escape Routing and Region Routingmentioning

confidence: 99%

Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB Routing

Yin,

Jin,

Chen

et al. 2023

IEEE Access

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“…Many studies in the literature have addressed these routing problems related to the PCBs. Some studies have proposed the heuristics algorithms to obtain a length matching routing (Zhang et al, 2015b) and others have used differential pair escape (Li et al, 2012(Li et al, , 2019, single signal escape routing (Wu & Wong, 2013) or both (Wang et al, 2014) for escape routing along with addressing the length matching problem. The most notable technique used for the PCB routing is optimization.…”

Section: Related Workmentioning

confidence: 99%

A dual model node based optimization algorithm for simultaneous escape routing in PCBs

Ali

Anjum

Zeeshan

2021

PeerJ Computer Science

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Simultaneous Escape Routing (SER) is the escaping of circuit pins simultaneously from inside two or more pin arrays. This is comparatively difficult as compared to routing in a single array and has not been addressed by previous studies. The increase in pin array complexity has made the manual SER in PCBs a very inefficient and tedious task and there surely is need for the automated routing algorithms. In this work, we propose network flow based optimal algorithm that uses integer linear program to solve SER problem and area routing problem in two stages. In the first stage, pins are escaped to the boundaries of pin arrays simultaneously. These escaped pins are connected with each other in the second stage. The proposed algorithm is tested for different benchmark sizes of grids and the results show that it is not only better in terms of routability but also outperforms existing state of the art algorithms in terms of time consumption. The existing algorithms either fails to achieve higher routability or have larger time complexities, whereas the proposed algorithm achieves 99.9% routability and is also independent of grid topology and component pin arrangement, which shows the superiority of proposed algorithm over the existing algorithms.

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A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints

Liu,

Lin,

Chen

et al. 2023

2023 60th ACM/IEEE Design Automation Conference (DAC)

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Mixed-Crossing-Avoided Escape Routing of Mixed-Pattern Signals on Staggered-Pin-Array PCBs

Cited by 10 publications

References 8 publications

Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB Routing

Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB Routing

A dual model node based optimization algorithm for simultaneous escape routing in PCBs

A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints

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