Mismatch sensitivity of a simultaneously latched CMOS sense amplifier

Sarpeshkar, Rahul; Wyatt, John L.; Lu, Nicky; Gerber, P. D.

doi:10.1109/4.90096

Cited by 43 publications

(11 citation statements)

References 5 publications

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“…The robustness is determined by the minimum voltage difference between two bit-lines that can be correctly sensed (input offset voltage). A lower sensing delay and smaller input offset voltage represent a better sense amplifier [14], [30].…”

Section: Voltage Mode Sense Amplifiersmentioning

confidence: 99%

A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET

Mukhopadhyay

Mahmoodi

Roy

2006

IEEE Trans. VLSI Syst.

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Abstract-Double-gate (DG) transistor has emerged as one of the most promising devices for nano-scale circuit design. In this paper, we propose a high-performance and robust sense-amplifier design using independent gate control in symmetric and asymmetric DG devices for sub-50-nm technologies. The proposed sense amplifier has better performance (30%-35% less sensing delay) and robustness (60%-80% less minimum input bit-differential for correct operation considering 10% worst case silicon thickness mismatch) compared to the connected gate design. Hence, the proposed design successfully demonstrates the benefit of using independent gate control in DG devices for efficient circuit design in sub-50-nm regime.

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Section: Voltage Mode Sense Amplifiersmentioning

confidence: 99%

A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET

Mukhopadhyay

Mahmoodi

Roy

2006

IEEE Trans. VLSI Syst.

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“…3-b), and the variation of threshold voltage [4] of the PSA_T transistors (shown as vth mismatch in Fig. 3-b).…”

Section: Stabilitymentioning

confidence: 99%

“…It works well throughout the entire simulation window. 4. The stability on variation of Vth when cell data is '0' (Fig.…”

Section: Stabilitymentioning

confidence: 99%

A new dual asymmetric bit-line sense amplifier for low-voltage dynamic random access memory

Noh

Kim

Lee

et al. 2013

IEICE Electron. Express

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This paper presents a new dual asymmetric bit-line sense amplifier to cope with the recent need for GND or VDD bit-line precharge scheme for improving bit-line sensing margin and speed of contemporary low-voltage DRAM. The existing GND or VDD bitline pre-charge schemes have some disadvantages in terms of power, area and practicality, compared to the conventional VDD/2 bit-line pre-charge scheme. Our proposed sense amplifier, which is composed of two asymmetric PMOS sense amplifiers and one symmetric NMOS sense amplifier for GND bit-line pre-charge scheme, and several circuit optimization techniques provide excellent results regarding to stability, speed, and power, while keeping the area overhead under 1% in the size of sense amplifier region. Compared to a conventional VDD/2 scheme, the charge sharing time, sensing time, and precharging time have been improved by 20%, 47%, and 20%, respectively and the increase of power consumption due to GND pre-charge scheme has been minimized to 22.2%.

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“…The first approaches were in the form of circuit optimization. These kinds of studies are circuit specific and are not easily generalizable [6]. Such approaches by themselves are no longer adequate in preventing mismatch, since most of the time, process variation effects are compensated in these optimizations instead of mismatch.…”

Section: Previous Work On Mismatchmentioning

confidence: 99%

On mismatch in the deep sub-micron era-from physics to circuits

Topaloglu¹,

Orailoglu²

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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Abstract-Rapid decrease in feature sizes has increasingly accentuated the importance of matching between transistors. Deep sub-micron designs will further emphasize the need to focus on the effects of mismatch. Furthermore, increased efforts on high level analog device modeling will necessitate accompanying mismatch simulation and measurement methods. The deep sub-micron era forces circuit designers to learn more about the physics and the technology of transistors. This study introduces a method and assists circuit designers in including this method in their traditional design flow of circuits. By proposing a solution to the problem of building a modeling bridge between transistor mismatch and circuit response to it, we hope to enable designers to incorporate low level mismatch information in their higher level design.

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Mismatch sensitivity of a simultaneously latched CMOS sense amplifier

Cited by 43 publications

References 5 publications

A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET

A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET

A new dual asymmetric bit-line sense amplifier for low-voltage dynamic random access memory

On mismatch in the deep sub-micron era-from physics to circuits

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