Minimizing WCET for Real-Time Embedded Systems via Static Instruction Cache Locking

Liu, Tiantian; Li, Minming; Xue, Chun Jason

doi:10.1109/rtas.2009.11

Cited by 50 publications

(52 citation statements)

References 6 publications

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“…The work in this paper is orthogonal to many existing proposals that reduce WCET such as compilation optimization [10]- [12] and cache locking mechanism [13]. And it is different from existing task scheduling and mapping work in three aspects.…”

Section: Related Workmentioning

confidence: 99%

Cache-Aware Cooperative Task Mapping in Multi-core Real-Time Systems

Wang¹,

Ni²,

Jicheng³

et al. 2016

IJIEE

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Abstract-Program execution can be accelerated with efficient use of cache in real-time systems. And each program has its own instruction access pattern, which causes uneven distribution of accesses to the sets of instruction cache. In multi-core real-time systems, mapping tasks with similar instruction access patterns to the same core will incur massive conflicts and degrade the utilization of the cache. This paper proposes a cache-aware cooperative task mapping method to improve system efficiency in multi-core real-time systems. Our method quantifies the access frequency of instruction cache sets for each task, and then select tasks with complementary distributions to run on the same core, which can reduce inter-task interference and shorten the cache refill delay during context switch. Evaluation results show that the utilization of the system is improved by about 8.92% with the method.

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Section: Related Workmentioning

confidence: 99%

Cache-Aware Cooperative Task Mapping in Multi-core Real-Time Systems

Wang¹,

Ni²,

Jicheng³

et al. 2016

IJIEE

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“…Most cache locking techniques aimed at improving the WCET employ static cache locking [9], [15], [18], [7]. Static locking loads and locks the memory blocks at program startup, and the locked content remains unchanged throughout the program execution.…”

Section: Introductionmentioning

confidence: 99%

“…Static locking loads and locks the memory blocks at program startup, and the locked content remains unchanged throughout the program execution. Most static locking techniques use full cache locking [9], [15], [18] where the entire cache is locked. However, full locking does not allow the unlocked memory blocks to use the cache and exploit their locality, and thus may introduce negative impact on the overall WCET.…”

Section: Introductionmentioning

confidence: 99%

WCET-Centric dynamic instruction cache locking

Ding¹,

Liang²,

Mitra³

2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-Cache locking is an effective technique to improve timing predictability in real-time systems. In static cache locking, the locked memory blocks remain unchanged throughout the program execution. Thus static locking may not be effective for large programs where multiple memory blocks are competing for few cache lines available for locking. In comparison, dynamic cache locking overcomes cache space limitation through timemultiplexing of locked memory blocks. Prior dynamic locking technique partitions the program into regions and takes independent locking decisions for each region. We propose a flexible loopbased dynamic cache locking approach. We not only select the memory blocks to be locked but also the locking points (e.g., loop level). We judiciously allow memory blocks from the same loop to be locked at different program points for WCET improvement. We design a constraint-based approach that incorporates a global view to decide on the number of locking slots at each loop entry point and then select the memory blocks to be locked for each loop. Experimental evaluation shows that our dynamic cache locking approach achieves substantial improvement of WCET compared to prior techniques.

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“…Thus, locking the entire cache resolves the problem of timing unpredictability. More importantly, by carefully choosing the memory blocks to be locked, WCET estimate can be reduced compared to cache modeling techniques without locking [6,14].…”

Section: Introductionmentioning

confidence: 99%

“…Recently, a heuristic [6] and an optimal solution [14] have been proposed to minimize the WCET via static instruction cache locking. These existing techniques make an implicit but important de- cision of locking the entire cache.…”

Section: Introductionmentioning

confidence: 99%

WCET-centric partial instruction cache locking

Ding

Liang

Mitra

2012

Proceedings of the 49th Annual Design Automation Conference

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Caches play an important role in embedded systems by bridging the performance gap between high speed processors and slow memory. At the same time, caches introduce imprecision in Worst-case Execution Time (WCET) estimation due to unpredictable access latencies. Modern embedded processors often include cache locking mechanism for better timing predictability. As the cache contents are statically known, memory access latencies are predictable leading to precise WCET estimates. Moreover, by carefully selecting the memory blocks to be locked, WCET estimate can be reduced compared to cache modeling without locking. Existing static instruction cache locking techniques strive to lock the entire cache to minimize the WCET. We observe that such aggressive locking mechanisms may have negative impact on the overall WCET as some memory blocks with predictable access behavior get excluded from the cache. We introduce a partial cache locking mechanism that has the flexibility to lock only a fraction of the cache. We judiciously select the memory blocks for locking through accurate cache modeling that determines the impact of the decision on the program WCET. Our synergistic cache modeling and locking mechanism achieves up to 68% reduction in WCET for a large number of embedded benchmark applications.

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Minimizing WCET for Real-Time Embedded Systems via Static Instruction Cache Locking

Cited by 50 publications

References 6 publications

Cache-Aware Cooperative Task Mapping in Multi-core Real-Time Systems

Cache-Aware Cooperative Task Mapping in Multi-core Real-Time Systems

WCET-Centric dynamic instruction cache locking

WCET-centric partial instruction cache locking

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