Min-cost flow-based algorithm for simultaneous pin assignment and routing

Xiang, Hua; Tang, Xiaoping; Wong, D.F.

doi:10.1109/tcad.2003.814258

Cited by 16 publications

(12 citation statements)

References 15 publications

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“…For ICs, the pin assignment of macro blocks is usually optimized with regard to routability during placement [3][4], buffer planning [5] or routing [6]. Pin assignment approaches for PCBs and MCMs can be found in [7][8] [9][10].…”

Section: The Pin Assignment Problemmentioning

confidence: 99%

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Universal Methodology to Handle Differential Pairs during Pin Assignment

Meister¹,

Lienig²,

Thomke³

2010

IFIP Advances in Information and Communication Technology

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Abstract. Differential signaling has been a major challenge in design automation. The routing of differential pairs requires a suitable pin assignment of the respective nets. However, current automatic pin assignment algorithms lack the ability to consider differential pairs. We present a methodology to include differential pairs during pin assignment. Our solution can be applied to automatic or manual pin assignment processes without changing the methodologies already in place. This universality is achieved by using any established pin assignment approach as a black box, which is extended by pre and post processing steps. Extensive studies in industrial design flows show that our differential pair methodology does not compromise pin assignment quality with the added benefit of effective differential pair allocations.

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Section: The Pin Assignment Problemmentioning

confidence: 99%

“…It is further possible to integrate pin assignment into the global [16] and/or detailed routing phase. By integrating pin assignment into global routing, it can be adapted to the global requirements of routing, whereas a combination with detailed routing would support local adjustments of the pin assignment.…”

Section: Contextmentioning

confidence: 99%

Universal Methodology to Handle Differential Pairs during Pin Assignment

Meister¹,

Lienig²,

Thomke³

2010

IFIP Advances in Information and Communication Technology

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show abstract

“…2(b) and (c), respectively. Different designs incur different routing costs; therefore, solving the internal Steiner tree problem would help VLSI designers find the minimum routing cost in the ECO step [26,34]. There are some other practical applications.…”

Section: Introductionmentioning

confidence: 99%

The internal Steiner tree problem: Hardness and approximations

Huang

Lee

Gao

et al. 2013

Journal of Complexity

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The internal Steiner tree problem Design and analysis of algorithms a b s t r a c t Given a graph G = (V , E) with a cost function c : E → R + and a vertex subset R ⊂ V , an internal Steiner tree is a Steiner tree that contains all the vertices in R, and such that each vertex in R must be an internal vertex. The internal Steiner tree problem involves finding an internal Steiner tree T whose total costIn this paper, we first show that the internal Steiner tree problem is MAX SNP-hard. We then present a (2ρ + 1)-approximation algorithm for solving the problem on complete graphs, where ρ is an approximation ratio for the Steiner tree problem. Currently, the best-known ρ is ln 4+ϵ < 1.39. Moreover, for the case where the cost of each edge is restricted to being either 1 or 2, we present a 9 7 -approximation algorithm for the problem.

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“…As a result, it is quite necessary to optimize the total via number. Under the circumstances, many thermal aware TSVplanning and routing technologies were proposed [9,[13][14][15][16], aiming to reduce total via number and total wire length. However, there are two main disadvantages in these researches.…”

Section: Introductionmentioning

confidence: 99%

Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs

Wang

Dong

et al. 2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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3D IC has become an attractive technology as it decreases interconnection distance and improves performance. However, it is faced with heat dissipation and temperature problem seriously. The high temperature will increase the interconnection delay, and lead to degradation of performance. Through-silicon-via (TSV) has been shown as an effective way to optimize heat distribution. However, the distribution of TSVs will potentially influence the interconnection delay. In this paper, we propose a performance-driven 3D TSV-planning (3D-PTSP) algorithm, which can generate good TSV distribution, to improve temperature. The thermal effects on critical path delay are analyzed with leakage power-temperature-delay dependence considered. A priority based TSV redistribution algorithm and network flow based signal via allocation algorithm help to improve both TSV number and critical path delay without increasing temperature. Experimental results show that the proposed method can improve total via number by 8.9% and reduce critical path delay by 15.8%.

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Min-cost flow-based algorithm for simultaneous pin assignment and routing

Cited by 16 publications

References 15 publications

Universal Methodology to Handle Differential Pairs during Pin Assignment

Universal Methodology to Handle Differential Pairs during Pin Assignment

The internal Steiner tree problem: Hardness and approximations

Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs

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