Methodology for standard cell compliance and detailed placement for triple patterning lithography

Abstract

As the feature size of semiconductor process further scales to sub-16nm technology node, triple patterning lithography (TPL) has been regarded one of the most promising lithography candidates. M1 and contact layers, which are usually deployed within standard cells, are most critical and complex parts for modern digital designs. Traditional design flow that ignores TPL in early stages may limit the potential to resolve all the TPL conflicts. In this paper, we propose a coherent framework, including standard cell compliance and detailed placement to enable TPL friendly design. Considering TPL constraints during early design stages, such as standard cell compliance, improves the layout decomposability. With the pre-coloring solutions of standard cells, we present a TPL aware detailed placement, where the layout decomposition and placement can be resolved simultaneously. Our experimental results show that, with negligible impact on critical path delay, our framework can resolve the conflicts much more easily, compared with the traditional physical design flow and followed layout decomposition.

Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography

“…LELELE type TPL technology [8][9][10][11][12][13][14][15][16][17][18] in which litho-etch process is repeated three times is often discussed in literature. However, it suffers from native conflict and overlay problems.…”

“…Triple patterning lithography (TPL) is one of the most promising techniques in the 14 nm logic node and beyond. In order to realize a target pattern, various types of techniques including design for manufacturability, such as LELE type double patterning lithograph [1][2][3][4][5][6][7], LELELE type TPL [8][9][10][11][12][13][14][15][16][17][18], LELECUT type TPL [19], and side wall process [20], are used in addition to a basic litho-etch process with optimized mask. These techniques are summarized in [21,22].…”

Toward Unidirectional Routing Closure in Advanced Technology Nodes

“…The industrial routine for standard cell design still follows handcrafted design and optimization, which allows occasional two-dimensional layout patterns on metal-1 (M1) layer and below through extensive engineering changing efforts [33], [54]. This makes the standard cell design and placement stages partic- dpan@ece.utexas.edu ularly important to resolve manufacturing constraints, especially coloring, on M1 layer and below [14], [17], [19], [74]. In the routing phase, for upper metal layers with relaxed pitches and low metal densities, each layer has a preferred routing direction and two-dimensional routing patterns, i.e., wire bending, can be used to provide flexible routing solutions.…”

Comprehensive Performance Analysis of Interconnect Variation by Double and Triple Patterning Lithography Processes

“…To resolve BEOL patterning problems, several pitch splitting techniques have been proposed and considered as efficient solutions [2][3][4][5][6][7][8]. Double patterning lithography (DPL), or litho-etch-litho-etch (LELE), has been used for 20-nm logic nodes to pattern interconnect dimensions less than 100 nm [4,9,10].…”