Memory characteristics of ordered Co/Al2O3 core-shell nanocrystal arrays assembled by diblock copolymer process

Abstract

An ordered Co/ Al 2 O 3 core-shell nanocrystal ͑NC͒ nonvolatile memory device was fabricated. Self-assembled diblock copolymer process aligned the NCs with uniform size. Co/ Al 2 O 3 core-shell NCs were formed using atomic layer deposition of Al 2 O 3 before and after the ordered Co NC formation. Compared to Co NC memory, Co/ Al 2 O 3 core-shell NC memory shows improved retention performance without sacrificing writing and erasing speeds.

Improved performance of non-volatile memory with Au-Al2O3 core-shell nanocrystals embedded in HfO2 matrix

“…In the past decade, tremendous efforts have been invested into research of nanocrystal (NC) memories from materials and structures. Semiconductor nanocrystals such as Si, 1 Ge, 2 metal nanocrystals such as Al, 3,4 Ag, 5 Ni, 6 W, 7-9 Pt, 10 Au, [11][12][13][14] Ru, 15 Co, 16,17 ,Ir, 18 and oxide nanocrystals such as IrO x , 19 RuO (Ref. 20) have been reported.…”

Oxide Nanostructures Hyperbranched with Thin and Hollow Metal Shells for High‐Performance Nanostructured Battery Electrodes

“…However, it is still a great challenge to fabricate high‐quality oxide/metal core‐branch nanoarrays directly on conductive substrates. Anodic aluminum oxide (AAO) and block copolymer templates have been employed as effective templates for the synthesis of oxide/metal core‐shell nanowires or tubes, such as Ni/Al 2 O 3 , Co/Al 2 O 3 , Ni/TiO 2 , Ni/V 2 O 5 , Ni/NiO, Bi/Bi 2 O 3 , and Co/NiO/Ni . However, these syntheses are limited to simple geometry or flat surfaces and hence are difficult for large‐scale growth of active materials on nonplanar substrates.…”

Temperature-dependent electron transport in highly ordered Co/Al2O3 core-shell nanocrystal memory synthesized with di-block co-polymers

“…17,18 Recently, several approaches to fabricate high density core-shell NC memory devices have been implemented to achieve improved performance. 19,20 Co/Al 2 O 3 core-shell NC memory, using Fowler-Nordheim (FN) tunneling for program/ erase (P/E) operation, has been demonstrated to achieve enhanced retention performance without sacrificing P/E speed. Uniformly distributed NCs assembled by di-block copolymer were employed in the devices, which is promising for improving device performance, scalability, and manufacturability.…”

“…Uniformly distributed NCs assembled by di-block copolymer were employed in the devices, which is promising for improving device performance, scalability, and manufacturability. 20 In most nonvolatile memory works, the P/E characteristics are usually investigated at room temperature, and direct experimental observations of temperature dependent P/E characteristics are very rare. [21][22][23][24] The ambient temperature can vary significantly during operation of nonvolatile memory, therefore it is essential to investigate the temperature effect on the memory performance and to estimate the performance of a memory embedded circuit under different ambient temperatures.…”

“…The detailed fabrication process was reported elsewhere. 20 Figures 1(b) and 1(c) show the atomic force microscope (AFM) images of the Co NCs on top of the Al 2 O 3 layer with di-block copolymer and core-shell NCs, respectively. The NC arrays are well ordered with uniform size and spacing between particles, resulting in a density of $5 Â 10 11 NCs/cm 2 .…”