Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays

Kim, Yongjoo; Lee, Jong-Eun; Shrivastava, Aviral; Yoon, Jong‐Won; Paek, Yunheung

doi:10.1007/978-3-642-11515-8_14

Cited by 14 publications

(8 citation statements)

References 12 publications

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“…Recent studies [16], [17] propose various solutions to reduce the data transfer overhead between the system memory, a local memory, and the processing elements from the architecture and compiler perspective. In particular, the ADRES architecture [18] allows tight coupling between main processor and CGRA, by reconfiguring some processing elements of the CGRA as a VLIW processor.…”

Section: Related Workmentioning

confidence: 99%

CRM: Configurable Range Memory for Fast Reconfigurable Computing

Paek

Lee

Choi

2011

2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PHD Forum

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Application-specific hardware and reconfigurable processors can dramatically speed up compute-intensive kernels of applications, offloading the burden of main processor. To minimize the communication overhead in such a coprocessor approach, the two processors can share an on-chip memory, which may be considered by each processor as a scratchpad memory. However, this setup poses a significant challenge to the main processor, which now must manage data on the scratchpad explicitly, often resulting in superfluous data copy. This paper presents an enhancement to scratchpad, called Configurable Range Memory (CRM), that can reduce the need for explicit management and thus reduce data copy and promote data reuse on the shared memory. Our experimental results using benchmarks from DSP and multimedia applications demonstrate that our CRM architecture can significantly reduce the communication overhead compared to the architecture without shared memory, while not requiring explicit data management.

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Section: Related Workmentioning

confidence: 99%

CRM: Configurable Range Memory for Fast Reconfigurable Computing

Paek

Lee

Choi

2011

2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PHD Forum

Self Cite

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“…For reconfigurable architectures that allow one cycle context switch such as ADRES [5], a variant of modulo scheduling can be used to find quality mappings within reasonable time. Subsequently memory issues are recognized as a dominant problem, making it necessary to consider data mapping in addition to compute-operation mapping during scheduling [6,7]. Data distribution and mapping in the context of the RAW machine is considered in [8].…”

Section: Related Workmentioning

confidence: 99%

Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture

Kim

Lee

et al. 2012

Lecture Notes in Computer Science

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Abstract. Reconfigurable Architecture (RA), which provides extremely high energy efficiency for certain domains of applications, have one problem that current mapping algorithms for it do not scale well with the number of cores. One approach to this problem is using SIMD (Single Instruction Multiple Data) paradigm. However, SIMD can complicate the mapping problem by adding an additional dimension, i.e., iteration mapping, to the already inter-dependent problems of data mapping and operation mapping, and can significantly affect performance through memory bank conflicts. In this paper we introduce SIMD reconfigurable architecture, which allows for SIMD mapping at multiple levels of granularity, and investigate ways to minimize bank conflicts in a SIMD reconfigurable architecture with the related sub-problems taken into consideration. We further present data tiling and evaluate a conflict-free scheduling algorithm as a way to eliminate bank conflicts for a certain class of iteration and data mapping.

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“…The existing data transfer mechanism between RCA and local memory can be classified into types of explicit [8]- [12] or implicit [13]- [15] approaches. Whether the RCAs have the ability of fetching the computing data initiatively is the main difference between these two.…”

Section: Introductionmentioning

confidence: 99%

“…Whether the RCAs have the ability of fetching the computing data initiatively is the main difference between these two. Those reconfigurable cells (RCs) [8], [9] or simple programmable processors [11], [12] that explicitly access the memory with a certain flexibility are easy to program. However, their operations of load/store and the calculation of data address consume a considerable number of RCs.…”

Section: Introductionmentioning

confidence: 99%

“…Explicit CGRAs of ADRES [9] typically hide the latency of memory accesses by module mapping, but multiaccess requirements in a queue may result in stalls of the system. Others that implement multi-bank local memory [8] have to deal with data transfer between different banks respectively. These operations increase the latency and number of memory accesses thus greatly impact the performance of data transfer.…”

Section: Introductionmentioning

confidence: 99%

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A Data Prefetch and Reuse Strategy for Coarse-Grained Reconfigurable Architectures

et al. 2013

IEICE Trans. Inf. & Syst.

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SUMMARYThe Coarse Grained Reconfigurable Architectures (CGRAs) are proposed as new choices for enhancing the ability of parallel processing. Data transfer throughput between Reconfigurable Cell Array (RCA) and on-chip local memory is usually the main performance bottleneck of CGRAs. In order to release this stress, we propose a novel data transfer strategy that is called Heuristic Data Prefetch and Reuse (HDPR), for the first time in the case of explicit CGRAs. The HDPR strategy provides not only the flexible data access schedule but also the high data throughput needed to realize fast pipelined implementations of various loop kernels. To improve the data utilization efficiency, a dual-bank cache-like data reuse structure is proposed. Furthermore, a heuristic data prefetch is also introduced to decrease the data access latency. Experimental results demonstrate that when compared with conventional explicit data transfer strategies, our work achieves a significant speedup improvement of, on average, 1.73 times at the expense of only 5.86% increase in area.

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Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays

Cited by 14 publications

References 12 publications

CRM: Configurable Range Memory for Fast Reconfigurable Computing

CRM: Configurable Range Memory for Fast Reconfigurable Computing

Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture

A Data Prefetch and Reuse Strategy for Coarse-Grained Reconfigurable Architectures

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