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Cited by 14 publications
(8 citation statements)
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“…Recent studies [16], [17] propose various solutions to reduce the data transfer overhead between the system memory, a local memory, and the processing elements from the architecture and compiler perspective. In particular, the ADRES architecture [18] allows tight coupling between main processor and CGRA, by reconfiguring some processing elements of the CGRA as a VLIW processor.…”
Section: Related Workmentioning
confidence: 99%
“…Recent studies [16], [17] propose various solutions to reduce the data transfer overhead between the system memory, a local memory, and the processing elements from the architecture and compiler perspective. In particular, the ADRES architecture [18] allows tight coupling between main processor and CGRA, by reconfiguring some processing elements of the CGRA as a VLIW processor.…”
Section: Related Workmentioning
confidence: 99%
“…For reconfigurable architectures that allow one cycle context switch such as ADRES [5], a variant of modulo scheduling can be used to find quality mappings within reasonable time. Subsequently memory issues are recognized as a dominant problem, making it necessary to consider data mapping in addition to compute-operation mapping during scheduling [6,7]. Data distribution and mapping in the context of the RAW machine is considered in [8].…”
Section: Related Workmentioning
confidence: 99%
“…The existing data transfer mechanism between RCA and local memory can be classified into types of explicit [8]- [12] or implicit [13]- [15] approaches. Whether the RCAs have the ability of fetching the computing data initiatively is the main difference between these two.…”
Section: Introductionmentioning
confidence: 99%
“…Whether the RCAs have the ability of fetching the computing data initiatively is the main difference between these two. Those reconfigurable cells (RCs) [8], [9] or simple programmable processors [11], [12] that explicitly access the memory with a certain flexibility are easy to program. However, their operations of load/store and the calculation of data address consume a considerable number of RCs.…”
Section: Introductionmentioning
confidence: 99%
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