Memory access optimization in compilation for coarse-grained reconfigurable architectures

Abstract

Coarse-grained reconfigurable architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and moving the complexity to application mapping. One major challenge comes in the form of data mapping. For reasons of power-efficiency and complexity, CGRAs use multibank local memory, and a row of PEs share memory access. In order for each row of the PEs to access any memory bank, there is a hardware arbiter between the memory requests generated by the PEs and the banks of the local memory. However, a fundamental restriction remains in that a bank cannot be accessed by two different PEs at the same time. We propose to meet this challenge by mapping application operations onto PEs and data into memory banks in a way that avoids such conflicts. To further improve performance on multibank memories, we propose a compiler optimization for CGRA mapping to reduce the number of memory operations by exploiting data reuse. Our experimental results on kernels from multimedia benchmarks demonstrate that our local memory-aware compilation approach can generate mappings that are up to 53% better in performance (26% on average) compared to a memoryunaware scheduler.

A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses

“…In Kim et al [2011], a general analysis of memory access support issues for a generic family of loosely coupled, coarse-grained accelerators is performed. The accelerators have local single-port memory banks.…”

Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units

“…ese systems can be classi�ed based on the level of coupling between the RPU and the GPP, the granularity of the RPU, the capability to support memory operations, and on the type of approach: online or offline. Although there have been many authors focusing on partitioning and compilation of applications to systems consisting of an GPP and an RPU (see, e.g., [24]), we focus here on the approaches that consider runtime efforts. Related to our work are the approaches proposed by Warp [4,10], AMBER [12,13], CCA [5,11], and DIM [6,14].…”

Hybrid compile and run-time memory management for a 3D-stacked reconfigurable accelerator

“…Several of them target instruction set extensions like [15,4]. Recently, the main objective becomes the mapping of the sole loops for reducing the reconfiguration or initialization costs [1,19,21,10,9]. Our mapping approach too is dedicated to the loops.…”