Measurements and Simulations of Low Dark Count Rate Single Photon Avalanche Diode Device in a Low Voltage 180-nm CMOS Image Sensor Technology

Leitner, T.; Feiningstein, Amos; Turchetta, R.; Coath, R.; Chick, Steven; Visokolov, G.; Savuskan, Vitali; Javitt, M.; Gal, Lior; Brouk, Igor; Bar-Lev, Sharon; Nemirovsky, Y.

doi:10.1109/ted.2013.2259172

Cited by 55 publications

(26 citation statements)

References 19 publications

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“…At the same time, however, there are also some disadvantages: lower and narrower PDP as well as higher tunneling noise due to higher doping concentrations. In order to compare performance of the proposed SPAD fabricated in 140-nm SOI CMOS technology to the literature in similar technology nodes, we restricted our attention to all reported substrate-isolated SPADs implemented in a feature size smaller than 250 nm [4,[13][14][15][16][17][18]. Consequently, SPADs fabricated in 350-nm CMOS technology are excluded in this comparison, although they exhibit good performance [19][20][21].…”

Section: Comparison With the State-of-the-art Cmos Spadsmentioning

confidence: 99%

“…The reason for ruling out non-substrate-isolated SPADs is that they are not suitable for array configurations and for integration with electronic circuits in the same substrate due to high optical crosstalk and electrical interference from digital circuits [4,22,23]. [14,15]. Compared to other CMOS SPADs, the SOI CMOS SPAD exhibits medium PDP at short wavelengths but overperforms most SPADs in the literature above 750 nm.…”

Section: Comparison With the State-of-the-art Cmos Spadsmentioning

confidence: 99%

“…10. Charbon, 65-nm CMOS [18] Niclass, 130-nm CIS [15] Gersback, 130-nm CIS [16] This work, 140-nm SOI CMOS Veerappan, 180-nm CMOS [4] Leitner, 180-nm CIS [14] Wu, 250-nm HV CMOS [13] Richardson, 130-nm CIS [17] Photon detection probability [ The performance of the SPAD implemented in the standard 140-nm SOI CMOS technology reported in this paper is summarized in Table 1. In addition, it reports a performance comparison with substrate-isolated SPADs fabricated in advanced CMOS technologies (140-nm technology nodes and below).…”

Section: Comparison With the State-of-the-art Cmos Spadsmentioning

confidence: 99%

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A first single-photon avalanche diode fabricated in standard SOI CMOS technology with a full characterization of the device

Lee¹,

Sun²,

Charbon³

2015

Opt. Express

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This paper reports on the first implementation of a single-photon avalanche diode (SPAD) in standard silicon on insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. The SPAD is realized in a circular shape, and it is based on a P + /N-well junction along with a P-well guard-ring structure formed by lateral diffusion of two closely spaced N-well regions. The SPAD electric-field profile is analyzed by means of simulation to predict the breakdown voltage and the effectiveness of premature edge breakdown. Measurements confirm these predictions and also provide a complete characterization of the device, including current-voltage characteristics, dark count rate (DCR), photon detection probability (PDP), afterpulsing probability, and photon timing jitter. The SOI CMOS SPAD has a PDP above 25% at 490-nm wavelength and, thanks to built-in optical sensitivity enhancement mechanisms, it is as high as 7.7% at 850-nm wavelength. The DCR is 244 Hz/μm 2 , and the afterpulsing probability is less than 0.1% for a dead time longer than 200 ns. The SPAD exhibits a timing response without exponential tail and provides a remarkable timing jitter of 65 ps (FWHM). The new device is well suited to operate in backside illumination within complex three-dimensional (3D) integrated circuits, thus contributing to a great improvement of fill factor and jitter uniformity in large arrays. and W. Brockherde, "CMOS SPADs with up to 500 μm diameter and 55% detection efficiency at 420 nm," J.

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Section: Comparison With the State-of-the-art Cmos Spadsmentioning

confidence: 99%

Section: Comparison With the State-of-the-art Cmos Spadsmentioning

confidence: 99%

Section: Comparison With the State-of-the-art Cmos Spadsmentioning

confidence: 99%

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A first single-photon avalanche diode fabricated in standard SOI CMOS technology with a full characterization of the device

Lee¹,

Sun²,

Charbon³

2015

Opt. Express

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“…The use of CMOS pixels that can internally amplify the signal by utilizing the avalanche breakdown mechanism to improve the signal-to-noise characteristics represents an evolutionary step forward in CMOS-SPAD imaging technology, as outlined below [7][8][9][10][11].…”

Section: Cmos Image Sensors and Cmos-spadsmentioning

confidence: 99%

Gun muzzle flash detection using CMOS sensors

Merhav

Savuskan

Nemirovsky

2013

2013 IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems (COMCAS 2013)

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This study focuses on the detection of muzzle flash detection of small arms using low cost silicon CMOS -based sensors and imagers. Two types of sensors are utilized: CMOS Image Sensors and CMOS-SPADs (Single Photon Avalanche Diodes). The detection approach is based on Near-Infrared (NIR) spectral features of muzzle flash originating from alkali metal flash suppressing additives in the gun powder. The spectral signature around wavelength of 760nm allows achieving adequate signal to noise ratio even in day light.

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“…Finally, Leitner and Hendersonin literature [8] and [9] ameliorated the performance of virtual guard ring. All these above efforts are beneficial to prevent from the premature edge breakdown of the avalanche diode.…”

Section: Introductionmentioning

confidence: 98%

High-Performance Structure of Guard Ring in Avalanche Diode for Single Photon Detection

Wang¹,

Wei²

2017

IJCNS

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Avalanche photon diode and avalanche diode array, working in Geiger mode, have single photon detection capability. The structure of guard ring is the key factor to avoid the premature edge breakdown of the avalanche diode and increase the maximum bias voltage. A new structure of the guard ring is proposed in this letter, in which the floating guard ring is put outside the p-well guard ring. Simulation results indicate that the maximum bias voltage of the proposed guard ring is higher than that of the state-of-the-art methods.

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Measurements and Simulations of Low Dark Count Rate Single Photon Avalanche Diode Device in a Low Voltage 180-nm CMOS Image Sensor Technology

Cited by 55 publications

References 19 publications

A first single-photon avalanche diode fabricated in standard SOI CMOS technology with a full characterization of the device

A first single-photon avalanche diode fabricated in standard SOI CMOS technology with a full characterization of the device

Gun muzzle flash detection using CMOS sensors

High-Performance Structure of Guard Ring in Avalanche Diode for Single Photon Detection

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