Maximizing the voltage and current capability of GaN FETs in a hard-switching converter

Research of Power Loop Layout and Parasitic Inductance in GaN Transistor Implementation

“…This is alleviated by the TIM enclosure thermal design proposed in [32], [33]. Thermal vias [13], [29], [30] Not applied Heat sink installation for top cooling device Thermal interface material attachment/enclosure method [15], [27], [31]- [34] V. CONCLUSIONS Power loop inductance in the GaN based converters is thoroughly investigated in this paper. Methodology of the power loop inductance modeling is illustrated step by step in 4 stages.…”

“…Several low inductance power loop layouts have been discussed in the prior-art research. Although these results vary in the transistor implementation, integration type (discrete device or power module) and converter topology, their optimization methods for the power loop layout can be classified into two major categories: length minimization [13]- [15] and magnetic flux cancellation [16]- [20]. Effectiveness of the prior-art layout methods is generally validated either by the FEA simulation results or by the percentage overshoot measured from the drain-source voltage.…”

A Comparison Review of the Resonant Gate Driver in the Silicon MOSFET and the GaN Transistor Application

“…The slew rate of the transistor switching must be well designed to guarantee the gating efficiency and reliability. For the conventional gate driver, two gate resistors with different resistance are respectively installed to the gate-on and gateoff path to protect the transistor from over-shoot breakdown, which is especially important for GaN transistor application as the lack of avalanche breakdown and the limited voltage tolerance [16], [48], [49]. The resonant gate driver with controllable slew rate is proposed in [47] for Silicon MOSFET application and further explored in [50] to be applied in GaN transistor application.…”

Multi-physic Analysis for GaN Transistor PCB Layout

“…2, compose the power loop inductance, which is resonant with the transistor output capacitor C p h and C p l during the switching transient. The optimal power loop effectively reduces the power loop inductance and thus reduces the drain-source voltage ringing during hard switching operation [12] [13] [14]. Several power loop layout designs have been discussed in [15] [16].…”