Material removal model for chemical–mechanical polishing considering wafer flexibility and edge effects

Seok, Jongwon; Sukam, Cyriaque P.; Kim, Andrew T.; Tichy, John; Cale, Timothy S.

doi:10.1016/j.wear.2004.01.011

Cited by 31 publications

(12 citation statements)

References 35 publications

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“…The spatial distribution correlates with the WIWNU observed in a single wafer, whereas the long-range temporal distribution correlates with the MRR decay and the resulting WTWNU over a batch of wafers. Seok et al [57] showed large changes in polishing removal rate near the wafer's edges (edge effects), as often seen in practice, with very uniform removal across most of the wafer surface. Kim et al [58] in a three-dimensional multiscale elastohydrodynamic lubrication (EHL) contact model showed that the contact force exerted on the wafer surface by asperities is nonuniform across the wafer, which implies nonuniformity in material removal.…”

Section: Review Of Modeling Of Pad Effects On Polishing Performancementioning

confidence: 92%

Pads for IC CMP

Wang

Paul

Kobayashi

et al. 2007

Microelectronic Applications of Chemical Mechanical Planarization

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The chemical-mechanical polishing or planarization (CMP) process is a complex interplay between the wafer and the consumables involved. The consumables include slurry, pad, conditioner, and so on. During polishing, the pad carries the slurry and delivers it to the wafer surface. It also transmits the normal and shear forces from the polisher to the wafer. Therefore, polishing pad plays a critical role in the CMP process and influences the outcomes such as material removal rate (MRR), within-wafer nonuniformity (WIWNU), wafer-to-wafer nonuniformity (WTWNU), step height reduction efficiency (SHRE), and defect counts.As the CMP process is a combination of mechanical and chemical processes, the polishing pad has to endure repeated mechanical stress and constant chemical attacks. The applied downforce and polishing-induced friction force cause various levels of compression and abrasion. Slurry components such as oxidizers and acids can react with different components of the pads. Thus the polishing pad must have sufficient mechanical integrity and chemical resistance to survive the rigors of polishing. Polishing pads must balance the needs of hardness, modulus for planarity, and strength to resist wear and tear during polishing. Pads must also be able to survive the aggressive slurry chemistry used in CMP polishing without degrading, delaminating, blistering, or warping, since CMP slurries for the polishing of interlevel dielectric (ILD) oxide layers are usually highly alkaline with pH as high as 11, and CMP slurries for the polishing of metal films are highly acidic Microelectronic Applications of Chemical Mechanical Planarization, Edited by Yuzhuo Li

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Section: Review Of Modeling Of Pad Effects On Polishing Performancementioning

confidence: 92%

Pads for IC CMP

Wang

Paul

Kobayashi

et al. 2007

Microelectronic Applications of Chemical Mechanical Planarization

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“…研磨减薄的优势是减薄速率可以超过 300 µm/min, 适合大批量生产 [87] ; 劣势是单纯的研磨减薄无法对薄膜厚度进行精确控制, 同时研磨过程中会引入应力, 当薄膜厚度小于 200 µm 时容易发生破碎. 除此之外, 借助化学机械抛光 [88] 以及纯化学腐蚀的方法也可去除背面衬底 [89,90] , 化学腐蚀减薄衬底的方法可以避免应力的引入, 缺点是速率较低. 因此, 一个理想的方法是首先通过机械研磨的手段将加工好器件的衬底减薄到 200 µm 左右, 随后借助化学手段将衬底刻蚀到所需厚度.…”

Section: 干法转移工艺可将单晶硅锗薄膜微米、纳米量级的微结构、图案高效转移到不同的柔性衬底上面图 2(b)unclassified

Transfer techniques for single-crystal silicon/germanium nanomembranes and their application in flexible electronics

Guo

Huang

et al. 2018

Sci. Sin.-Inf.

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“…This includes mechanical grinding [22,23] and chemical mechanical polishing. [23][24][25] Wafer thinning realized via the chemical etching through a wet chemical etching agent [26] or dry gas plasma chemical reactions with Si material. [27] However, a significant part of the original material is lost during the thinning process.…”

Section: Introductionmentioning

confidence: 99%

Fabrication of Crystalline Si Thin Films for Photovoltaics

Shen

Cabarrocas

et al. 2022

Physica Rapid Research Ltrs

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Crystalline Si (c‐Si) thin films have been widely studied for their application to solar cells and flexible electronics. However, their application at large scale is limited by their fabrication process. As reviewed in this paper, many approaches have been studied, but only some of them have been made into large‐scale industrial production. The standard wire sawing of Si ingots cannot be scaled down to produce thin c‐Si wafers and films due to the brittle nature of c‐Si material, the resulting significant thickness variations, and the waste of material. Therefore, techniques based on the kerf‐less processes including “top‐down” and “bottom‐up” approaches have been developed in recent decades. In this review, photovoltaic applications of thin c‐Si wafers with thicknesses ranging from 50 μm down to 1 μm are presented first. Then, methods to fabricate c‐Si thin films based on both approaches are detailed, including slim‐cut, “smart‐cut,” epi‐free, as well as various growth processes such as molecular beam epitaxy, liquid phase epitaxy, ion beam, and chemical vapor deposition processes at a wide range of growth temperatures, from 1000 °C down to 150 °C. The advantages and disadvantages of these methods are presented and compared.

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Material removal model for chemical–mechanical polishing considering wafer flexibility and edge effects

Cited by 31 publications

References 35 publications

Pads for IC CMP

Pads for IC CMP

Transfer techniques for single-crystal silicon/germanium nanomembranes and their application in flexible electronics

Fabrication of Crystalline Si Thin Films for Photovoltaics

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