MAMPSx: A design framework for rapid synthesis of predictable heterogeneous MPSoCs

Abstract

Abstract-HeterogeneousMultiprocessor System-on-Chips (HMPSoC) are becoming popular as a means of meeting energy efficiency requirements of modern embedded systems. However, as these HMPSoCs run multimedia applications as well, they also need to meet real-time requirements. Designing these predictable HMPSoCs is a key challenge, as the current design methods for these platforms are either semi-automated, non-predictable, or have limited heterogeneity.In this paper, we propose a design framework to generate and program HMPSoC designs in a rapid and predictable manner. It takes the application specifications and the architecture model as input and generates the entire HMPSoC, for FPGA prototyping, that meets the throughput constraints. The experimental results show that our framework can provide a conservative bound on the worst-case throughput of the FPGA implementation. We also present results of a case study that computes the area-power trade-offs of an industrial vision application. The entire design space exploration of all configurations was completed in 8 hours. A tool-chain targeting the Xilinx Zynq FPGA is also presented.

SPINE: From C loop-nests to highly efficient accelerators using Algorithmic Species

“…For SPINE, which uses the same skeleton template for all values of P , we observe a much flatter scaling. It also outperforms a manual implementation (described in [16]) that has an input buffer with equal width as the AXI interface and requires five cycles (4 load, 1 execute, non-pipelined) per execution of 128 parallel PEs. If this manual accelerator would perform only 32-parallel operations, only a single load-cycle would be required, and it would be at a point similar to P = 32 for SPINE.…”

(AS)2: Accelerator Synthesis using Algorithmic Skeletons for Rapid Design Space Exploration

“…The implementation target was the Zynq XC7Z045 FPGA device. Figure 5 shows the area-performance trade-offs for the three kernels using: (1) a single design point from a hand-coded RTL implementation [12], (2) a single design point from the Vivado OpenCV video library [9], (3) multiple design points (P 0 = 1..128) generated from naive C through HLS (HLS-C), and (4) multiple design points generated from C' through HLS using (AS) 2 . The post place-and-route results are presented.…”