Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors

Feng, Shuguang; Gupta, Shantanu; Ansari, Amin; Mahlke, Scott

doi:10.1007/978-3-642-11515-8_15

Cited by 30 publications

(11 citation statements)

References 18 publications

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“…Although technology scaling aggravates lifetime reliability and issues such as process variation become more severe, the heterogeneity of large CMPs can be a potential opportunity. Maestro, described in Feng et al [2010], is the CMP system with enhanced lifetime reliability based on recognition. By taking advantage of sensor feedback, Maestro formulates a wear out-centric scheduling that accomplished both global and local wear leveling.…”

Section: Scheduling/load Balancingmentioning

confidence: 99%

Lifetime Reliability Enhancement of Microprocessors

Hong

Lim

et al. 2015

ACM Comput. Surv.

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Ensuring lifetime reliability of microprocessors has become more critical. Continuous scaling and increasing temperatures due to growing power density are threatening lifetime reliability. Negative bias temperature instability (NBTI) has been known for decades, but its impact has been insignificant compared to other factors. Aggressive scaling, however, makes NBTI the most serious threat to chip lifetime reliability in today's and future process technologies. The delay of microprocessors gradually increases as time goes by, due to stress and recovery phases. The delay eventually becomes higher than the value required to meet design constraints, which results in failed systems. In this article, the mechanism of NBTI and its effects on lifetime reliability are presented, then various techniques to mitigate NBTI degradation on microprocessors are introduced. The mitigation can be addressed at either the circuit level or architectural level. Circuit-level techniques include design-time techniques such as transistor sizing and NBTI-aware synthesis. Forward body biasing, and adaptive voltage scaling are adaptive techniques that can mitigate NBTI degradation at the circuit level by controlling the threshold voltage or supply voltage to hide the lengthened delay caused by NBTI degradation. Reliability has been regarded as something to be addressed by chip manufacturers. However, there are recent attempts to bring lifetime reliability problems to the architectural level. Architectural techniques can reduce the cost added by circuit-level techniques, which are based on the worst-case degradation estimation. Traditional low-power and thermal management techniques can be successfully extended to deal with reliability problems since aging is dependent on power consumption and temperature. Self-repair is another option to enhance the lifetime of microprocessors using either core-level or lower-level redundancy. With a growing thermal crisis and constant scaling, lifetime reliability requires more intensive research in conjunction with other design issues. ACM Reference Format:Hyejeong Hong, Jaeil Lim, Hyunyul Lim, and Sungho Kang. 2015. Lifetime reliability enhancement of microprocessors: Mitigating the impact of negative bias temperature instability.

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Section: Scheduling/load Balancingmentioning

confidence: 99%

Lifetime Reliability Enhancement of Microprocessors

Hong

Lim

et al. 2015

ACM Comput. Surv.

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“…The most common technique employed for DRM is DVFS, possibly with a feedback controller. Dynamic wearout centric job scheduling in chip multiprocessor proposed in [7] employs a fine grained reliability management at the module-level of the cores. As these approaches focus only on the lifetime reliability, the peak temperature constraint is not considered.…”

Section: Related Workmentioning

confidence: 99%

Lifetime Reliability Aware Architectural Adaptation

Muthukaruppan

Mitra

2013

2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems

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Abstract-Relentless CMOS technology scaling has resulted in increased on-chip temperature leading to serious concerns about lifetime reliability of micro-processors. Though dynamic thermal management techniques can control peak temperature, they often fail to meet the reliability targets due to the complex interplay between temperature and reliability. In this paper, we propose a dynamic reliability management (DRM) technique that exploits architectural adaptation in conjunction with dynamic voltage/frequency scaling (DVFS). We employ an online Bayesian classifier that can efficiently detect the reliable configurations, while a performance prediction model selects the one with best performance among all the reliable configurations. We later extend our approach to meet both reliability and thermal constraints. Experimental results reveal that our adaptive DRM technique achieves reliability targets while reducing performance overhead by 42.30% compared to DVFS and 28.68% compared to DVFS with fetch gating.

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“…In particular, we target server-class multicore processors, where the operational model seeks to maximize processor utilization. In contrast to core-redundancy models [2], [3] where only a fraction of cores are utilized with many idle cores, we seek methods to control the core executions to improve lifetime reliability while fully utilizing resources. Cores experience different levels of stresses depending on the characteristics of parallel workloads, power states, thermal coupling behaviors, etc.…”

Section: Introductionmentioning

confidence: 99%

“…However, exploiting component redundancy underutilizes available resources and is also an expensive solution. Therefore, architectural approaches such as dynamic reliability management (DRM) [2], [4] have gained favor as a cost-effective approach to enhancing the lifetime reliability.…”

Section: Introductionmentioning

confidence: 99%

Architectural Reliability: Lifetime Reliability Characterization and Management ofMany-Core Processors

Song

Mukhopadhyay

Yalamanchili

2015

IEEE Comput. Arch. Lett.

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This paper presents a lifetime reliability characterization of many-core processors based on a full-system simulation of integrated microarchitecture, power, thermal, and reliability models. Under normal operating conditions, our model and analysis reveal that the mean-time-to-failure of cores on the die show normal distribution. From the processor-level perspective, the key insight is that reducing the variance of the distribution can improve lifetime reliability by avoiding early failures. Based on this understanding, we present two variance reduction techniques for proactive reliability management; i) proportional dynamic voltage-frequency scaling (DVFS) and ii) coordinated thread swapping. A major advantage of using variance reduction techniques is that the improvement of system lifetime reliability can be achieved without adding design margins or spare components.

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Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors

Cited by 30 publications

References 18 publications

Lifetime Reliability Enhancement of Microprocessors

Lifetime Reliability Enhancement of Microprocessors

Lifetime Reliability Aware Architectural Adaptation

Architectural Reliability: Lifetime Reliability Characterization and Management ofMany-Core Processors

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