Low voltage low power sub-threshold operational amplifier in 180nm CMOS

Yadav, Chetali; Prasad, Sunita

doi:10.1109/ssps.2017.8071560

Cited by 12 publications

(8 citation statements)

References 5 publications

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“…where VBS is the body to source voltage, Vth0 is the threshold voltage at room temperature (for VBS = 0V), and λD and λB are the DIBL and body effect coefficients respectively [10]. From (1) and ( 2), the equation for transconductance gm can be derived [11…”

Section: A Subthreshold Operationmentioning

confidence: 99%

Design and Comparative analysis of a Two-Stage Ultra-Low-Power Subthreshold Operational Amplifier in 180nm, 90nm, and 45nm technology

Nitundil

Singh

Balaji

et al. 2021

2021 Devices for Integrated Circuit (DevIC)

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In this paper, a two-stage ultra-low-power operational amplifier is designed, and a comparative analysis of the proposed subthreshold complementary amplifier is presented between 180nm, 90nm, and 45nm CMOS technology. The proposed operational amplifier is compared across several different parameters to determine the optimal design. It achieves a maximum gain of around 75 dB and a phase margin of 76°, dissipating just 140nW with a supply voltage of 0.5 V which is well suited for biomedical applications that require low power and high gain. The proposed operational amplifier has been designed using a SPICE-based circuit simulator.

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Section: A Subthreshold Operationmentioning

confidence: 99%

Design and Comparative analysis of a Two-Stage Ultra-Low-Power Subthreshold Operational Amplifier in 180nm, 90nm, and 45nm technology

Nitundil

Singh

Balaji

et al. 2021

2021 Devices for Integrated Circuit (DevIC)

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“…Firstly, the channel length modulation becomes more critical in the small process node and increases the difficulty of implementing current bias schemes for the amplifier. The output impedance is also reduced by draininduced barrier lowering (DIBL) [16], limiting the opamp gain. The amplifier design uses an increased channel length to counteract these effects.…”

Section: Design Challengesmentioning

confidence: 99%

“…where λ P1,2 = 1/(g mP1,2 r oP1,2 ) and λ N1,2 = 1/(g mN1,2 r oN1,2 ) are the DIBL parameter of M P1,2 and M N1,2 , respectively [16]. The g mP1,2 and g mN1,2 are the transconductance of input transistors M P1,2 and M N1,2 , respectively.…”

Section: B Circuit Implementationmentioning

confidence: 99%

Area and Power-Efficient Capacitively-Coupled Chopper Instrumentation Amplifiers in 28 nm CMOS for Multi-Channel Biosensing Applications

Pham

Nguyen

et al. 2021

IEEE Access

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This paper presents two designs of a capacitively-coupled chopper instrumentation amplifier (CCIA) successfully implemented in 28 nm CMOS for biopotential sensing applications. The first design is a compact CCIA using offset-blocking for chopping ripple reduction, DC servo loop (DSL) for electrode offset (V EOS ) suppression, and a high pass filter (HPF) for handling common-mode (CM) artifacts. An inverter-based self-biased input stage is used for noise and power efficiency. The two gain stages of the CCIA achieve a low-frequency open-loop gain > 80 dB. Realized in an area of 0.05 mm 2 , the CCIA handles V EOS up to 50 mV and tolerates CM artifacts up to 1.5 V pp . The CCIA achieves a mid-band gain of 39.5 dB with a 1 kHz bandwidth by consuming 1 µW. The integrated input-referred noise (IRN) over 200 Hz bandwidth is 2.15 µV rms . The second design presents a dual-channel CCIA (DCCIA) using an orthogonal frequency chopping for multi-sensor array applications. An inverter-based input stage is used for noise efficiency. The measured results show that the DCCIA achieves a low-frequency gain of 39.5 dB with a 3-dB bandwidth up to 1 kHz by consuming 0.71 µW per channel. The measured noise density is 136 nV/√Hz with an integrated noise of 2.67 µV rms over 200 Hz bandwidth. The DCCIA suppresses V EOS up to 50 mV using the DSL. Realized in a compact area of 0.04 mm 2 per channel, an excellent gain matching error of 0.29% is achieved with the crosstalk higher than 58 dB between the channels. This work is a measured report on the instrumentation amplifier using, to the best of the authors' knowledge, one of the smallest CMOS process nodes.INDEX TERMS Chopper instrumentation amplifier, nanometer-scale CMOS, biopotential, multi-channel, electrode offset, DC servo-loop, neural signal recording.

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“…Chaitali et al [11] designed for biomedical applications in which all the transistors are operated for low voltage low power applications' using in TSMC 180nm technology and simulation has done in the Cadence environment. The circuit generates 40db gain, 114KHZ UGB, 72deg phase margin, power dissipation is112nW with 0.8V battery.should be less than 5%.…”

Section: Literature Surveymentioning

confidence: 99%

A Versatile Design of Low Power and High-Speed Operational Amplifier using Nano Scale Transistors

Asharani*,

Chinnaaiah,

Keerthi

et al. 2020

IJITEE

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This paper illustrates the design of low power and high-speed operational Amplifier using Nanoscale Transistors. The proposed design introduces biasing block, for generating I=10uA for Channel length=180nm Technology. Adding biasing block to two-stages operational Amplifier current is constant i.e. there are no fluctuations in power supply, increase in bandwidth and power dissipation is less as compared the previous result. The design is simulated in p-spice tool and performed AC analysis. After analysis, the design achieved the parameter like Gain = 40db, Phase Margin=90º, Unity Gain Band Width=13MHz, Output Swing=0.1v to 1.7v and Power Dissipation=0.145mW.

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Low voltage low power sub-threshold operational amplifier in 180nm CMOS

Cited by 12 publications

References 5 publications

Design and Comparative analysis of a Two-Stage Ultra-Low-Power Subthreshold Operational Amplifier in 180nm, 90nm, and 45nm technology

Design and Comparative analysis of a Two-Stage Ultra-Low-Power Subthreshold Operational Amplifier in 180nm, 90nm, and 45nm technology

Area and Power-Efficient Capacitively-Coupled Chopper Instrumentation Amplifiers in 28 nm CMOS for Multi-Channel Biosensing Applications

A Versatile Design of Low Power and High-Speed Operational Amplifier using Nano Scale Transistors

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