Low Temperature Surface Cleaning of Silicon and Its Application to Silicon MBE

Abstract

A low temperature thermal cleaning method for Si molecular beam epitaxy (MBE) is proposed. This method consists of wet chemical treatment to eliminate carbon contaminants on Si substrates, thin oxide film formation to protect the clean Si surface from contamination during processing before MBE growth, and desorption of the thin oxide film under UHV. The passivative oxide can be removed at temperatures below 800~ It is confirmed that Si epitaxial growth can take place on substrates cleaned by this method and that high quality Si layers with dislocations of fewer than 100/cm ~ and high mobility comparable to good bulk materials are formed. Surface cleanliness, the nature of thin passivative oxide films, and cleaning processes are also studied by using such surface analytic methods as Auger elec tron spectroscopy, reflection high energy electron diffraction, and x-ray photoelectron spectroscopy.Si molecular beam epitaxy (Si-MBE) has been shown to produce device quality epitaxial Si films. This can, however, be obtained only when a clean silicon substrate surface is prepared before epitaxial growth. That is, contaminants on the substrate, such as oxide and carbide, prevent layer growth and become the main causes of crystal defects in the epitaxial layers. In order to provide clean surfaces and eliminate defect origins at interfaces, high temperature thermal etching at about 1200~ prior to epitaxial growth has been commonly used in an ultrahigh vacuum (UHV) (1-5). However, this technique causes undesirable impurity diffusion and changes the designed impurity concentration profile within th.e Si substrate. Furthermore, crystal defects, such as dislocations and stacking faults, tend to increase and slip lines are often generated across the Si substrate during high temperature treatment. Thus, it is important to find a low temperature surface cleaning method in which the temperature can be lowered to below 900~ Several studies have reported low temperature surface cleaning techniques. The methods used include ion sputtering (6, 7), laser annealing (8, 9), "galliation," in which the substrate is exposed to a gallium vapor beam at about 800~ substrate temperature in UHV (10), and exposure to a Si beam (11). Ion sputtering, however, produces undesirable radiation damage at the surface and point defects often remain even after annealing. Galliation is effective in removing silicon oxide, but complete removal of Ga atoms from the Si surface and no Ga diffusion into the Si substrate have not yet been fully confirmed. Also, for the ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 54.245.13.81

Uniform Si nano-dot fabrication using reconstructed structure of Si(110)

“…Surface contamination removal and surface oxidation were performed by using Shiraki's method. 33) We confirmed that the thickness of oxide layer estimated by X-ray photoemission spectroscopy (XPS) is 5.8 Å, and this is consistent with the reported thickness (5-8 Å). 33) The thinness allows electron tunneling, and this indicates the possibility of STM measurement even on an oxide Si surface.…”

“…The observed step height is consistent with the monolayer step one of Si(110), and this indicates that the monolayer step of Si (110) is visible through the oxide layer due to the thinness of the oxide layer formed by Shiraki's method. 33) An increase in the desorption time induces the formation of large circle-shaped voids [ Fig. 1(b)].…”

Formation of low-resistivity region in p-Si substrate of SiGe/Si episystem by remote-hydrogen plasma treatment

“…After chemically cleaning, the substrates were annealed at 750 °C for 2 h in the MBE chamber to remove the surface oxide, which is the process based on the Shiraki-Ishizaka method [7]. Then Si buffer layer with a thickness of 100 nm was deposited at 750 °C and subsequently SiGe single layer was grown at 500 °C without intentional doping.…”

Initial stages of SiGe epitaxy on Si(001) studied by scanning tunneling microscopy

“…This vicinal angle gives o an average terrace size of around 160 A, which was confirmed by the STM results. The Si(001) samples were first degreased and cleaned with a wet-chemical oxide etch-regrowth procedure [21] and mounted on degassed tantalum sample holders before introducing them into the UHV chamber. The samples were degassed in the UHV for approximately 10 h at 680°C by using an e-beam heater.…”