Low-resistivity poly-metal gate electrode durable for high-temperature processing

Akasaka, Y.; Sugitani, Suehiro; Nakajima, K.; Nakasugi, Tetsuro; Miyano, K.; Kasai, K.; Oyamatsu, H.; Kinugawa, M.; Takagi, Masami; Agawa, Kenichi; Matsuoka, F.; Kakumu, M.; Suguro, K.

doi:10.1109/16.543020

Cited by 35 publications

(12 citation statements)

References 4 publications

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“…The resulting TiSi x interface layer makes good ohmic contact with p+ and n+ poly-Si at the bottom. 4 The bottom WN x (x < 0 3) layer is changed to W by releasing nitrogen, 10 11 which reacts with Ti to become the TiN layer. The resulting TiN thin layer and as-deposited TiN layer may effectively prevent the out-diffusion of boron, which may minimize the poly depletion effect of p+ poly-Si.…”

Section: Methodsmentioning

confidence: 99%

“…1 2 Tungsten dual poly gate electrodes (W-DPG; W/barrier metals/n+ and p+ poly-Si) could be a good solution reducing gate sheet resistance (R s ). [3][4][5] Recently, a Ti/WN barrier metal stack was proposed to reduce contact resistiance on p+ polySi gate stacks with good gate oxide integrity (GOI) in order to reduce gate-induced resistance-capacitance (RC) delay. 6 However, issues associated with inherent high gate R s induced by physical vapor deposited tungsten with the Ti/WN barrier may affect sub-100 nm gate lengths in DRAM.…”

Section: Introductionmentioning

confidence: 99%

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Optimization of Tungsten Dual Poly-Metal Gates in Memory Devices with Ti/WN/WSiN Barrier Metal

Sung¹,

Park²,

Ahmed³

et al. 2013

j. nanosci. nanotech.

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Due to the demand of high-speed/high-density and low power application of memory devices, tungsten dual poly gate (W-DPG; W/barrier metals/n+ and p+ poly-Si) electrode could be a good solution in order to reduce gate sheet resistance (Rs). Process optimization is completed for a diffusion barrier metal in a W-DPG. A new noble WSiN layer is inserted between the Ti/WN barrier metal and the tungsten gate electrode to maintain large grain size of W deposited by physical vapor deposition. The annealed WSiN during post-processing changes into crystallized WSi(x) mixed with SiN, which can make vertical conductive path between top and bottom interface, contributing to low vertical contact resistance (Rc) and low gate Rs adequate for high speed requirement of memory device. The Ti/WN/WSiN barrier is found to have the same electrical performance, ring oscillator singal delay as complicated multi-layes barrier metal, Ti/WN/TiN/WSi(x)/WN reported earlier. Therefore, the gate stack can be optimized by introducing a simpler diffusion barrier metal.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Optimization of Tungsten Dual Poly-Metal Gates in Memory Devices with Ti/WN/WSiN Barrier Metal

Sung¹,

Park²,

Ahmed³

et al. 2013

j. nanosci. nanotech.

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“…[7][8][9][10] Tungsten (W) has the most attention among various materials as the next-generation word line to replace silicon, due to advantage such as high thermal stability, sheet resistance lower than 5 X/sq, uniform resistance per area regardless of pattern size, and excellent patterning properties due to the small grain size. [11][12][13][14] Other properties required for nanoscale patterning regarding factors such as contamination, morphology, resistance control, surface reaction, and patterning properties have been considered. 11,15 However, the oxidation of tungsten surfaces during processing is a critical problem that needs to be solved for the application of tungsten as the word line for nanoscale semiconductor devices.…”

Section: Introductionmentioning

confidence: 99%

“…[11][12][13][14] Other properties required for nanoscale patterning regarding factors such as contamination, morphology, resistance control, surface reaction, and patterning properties have been considered. 11,15 However, the oxidation of tungsten surfaces during processing is a critical problem that needs to be solved for the application of tungsten as the word line for nanoscale semiconductor devices.…”

Section: Introductionmentioning

confidence: 99%

Study on the oxidation and reduction of tungsten surface for sub-50 nm patterning process

Kim

Nam

Cho

et al. 2012

Journal of Vacuum Science &Amp; Technology A: Vacuum, Surfaces, and Films

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The oxidation characteristics of tungsten line pattern during the carbon-based mask-layer removal process using oxygen plasmas have been investigated for sub-50 nm patterning processes, in addition to the reduction characteristics of the WO x layer formed on the tungsten line surface using hydrogen plasmas. The surface oxidation of tungsten lines during the mask layer removal process could be minimized by using low-temperature (300 K) plasma processing for the removal of the carbon-based material. Using this technique, the thickness of WO x on the tungsten line could be decreased to 25% compared to results from high-temperature processing. The WO x layer could also be completely removed at a low temperature of 300 K using a hydrogen plasma by supplying bias power to the tungsten substrate to provide a activation energy for the reduction. When this oxidation and reduction technique was applied to actual 40-nm-CD device processing, the complete removal of WO x formed on the sidewall of tungsten line could be observed.

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“…[1][2][3][4][5][6][7][8][9] In order to fabricate a robust memory device, the reliability characteristics of the new gate electrode should be confirmed. One of the strategies for boosting the device speed is to replace the conventional tungsten polycide ͑WSi x / poly-Si͒ gate with tungsten polymetal ͑W/WN x / poly-Si͒ gate, because the tungsten polymetal gate electrode has more than five times lower sheet resistance than that of tungsten polycide.…”

Section: Introductionmentioning

confidence: 99%

Effect of gate hard mask and sidewall spacer structures on the gate oxide reliability of W∕WNx∕poly-Si gate MOSFET for high density DRAM applications

Lim¹,

Cho²,

Jang³

et al. 2005

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Articles you may be interested inImproved gate oxide integrity of strained Si n -channel metal oxide silicon field effect transistors using thin virtual substrates Atomic-layer-deposited silicon-nitride/SiO 2 stacked gate dielectrics for highly reliable pmetal-oxide-semiconductor field-effect transistorsWe have studied the effects of the gate hard mask and the gate spacer nitride film on the reliability of W/WN x / poly-Si gated devices. When the gate hard mask nitride film is used, severe degradation of the stress-induced leakage current ͑SILC͒ and the interface trap density ͑D it ͒ characteristics are observed in the large metal-oxide-semiconductor ͑MOS͒ capacitors. On the other hand, as the devices become smaller, the effects of the hard mask nitride film are relieved. The gate spacer stack plays a more critical role in the reliability of smaller devices. The oxide/nitride ͑ON͒ spacered devices exhibit better reliability in terms of SILC, D it , threshold voltage ͑V th ͒ shift, and transconductance ͑G m ͒ compared to those of the nitride/oxide/nitride ͑NON͒ spacered ones. These behaviors are explained by the mechanical stress of the nitride films.

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Low-resistivity poly-metal gate electrode durable for high-temperature processing

Cited by 35 publications

References 4 publications

Optimization of Tungsten Dual Poly-Metal Gates in Memory Devices with Ti/WN/WSiN Barrier Metal

Optimization of Tungsten Dual Poly-Metal Gates in Memory Devices with Ti/WN/WSiN Barrier Metal

Study on the oxidation and reduction of tungsten surface for sub-50 nm patterning process

Effect of gate hard mask and sidewall spacer structures on the gate oxide reliability of W∕WNx∕poly-Si gate MOSFET for high density DRAM applications

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