Low resistance Ti or Co salicided raised source/drain transistors for sub-0.13 μm CMOS technologies

Chao, Calvin Yi‐Ping; Violette, Katherine E.; Unnikrishnan, S.; Nandakumar, M.; Wise, R.; Kittl, J. A.; Hong, Q. Z.; Chen, I.-C.

doi:10.1109/iedm.1997.649474

Cited by 17 publications

(11 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…On the contrary, it is reported that the resistance of Co silicide decreases from 0.7 m to below as the linewidth decreases; reverse linewidth dependence resulting from T-shaped gates is due to lateral Si overgrowth. 8 Similar phenomena were observed reproducibly in our Co silicidation studies, aimed at investigating the effects of residual rapid thermal oxide ͑RTO͒ on the formation of CoSi 2 and its properties. Influencing factors and the cause of phenomena were analyzed.…”

supporting

confidence: 77%

The Effects of Residual RTOs on Formation of CoSi[sub 2] and Its Properties for 0.18 μm CMOS

Lee

2004

J. Electrochem. Soc.

View full text Add to dashboard Cite

0.18 m complementary metal oxide semiconductors ͑CMOS͒ have been investigated considering its formation regions and process parameters such as polycrystalline structure and grain size, kinds of dopant, and integration schemes. Having a columnar-type polycrystalline Si, strong linewidth dependence of the sheet resistance was observed in the pϩ polycrystalline regions but not in the nϩ polycrystalline regions or the nϩ/pϩ diffusion regions. The same results were also observed when a granular-type polycrystalline Si was deposited as a gate material. The sheet resistance of CoSi 2 in the pϩ polycrystalline regions having a granular-type polycrystalline Si is higher than that of a columnar-type polycrystalline Si at all gate lengths. These results were found to be due to oxide that resided on the surface of polycrystalline Si in the pϩ polycrystalline regions and due to the larger area of grain boundary. An alternative integration has no linewidth dependence in any silicided regions down to 0.15 m gate length through removing the rapid thermal oxide ͑RTO͒ completely, which was used to block the dopants' out-diffusion from the source/drain and gate during the source/drain annealing that was processed before the cobalt deposition. Confirmation of these results was processed through lengthening the time of the diluted HF precleaning step to remove the RTO completely.The self-aligned silicide ͑SALICIDE͒ process forms through the solid-state reaction between Si and metal, lowering sheet resistance of gate and diffusion regions ͑source/drain͒ of complementary metal oxide semiconductor ͑CMOS͒ devices. It is used as local interconnects to reduce series resistance of the devices, 1 resulting in a higher switching speed and drive current for the devices. 2,3 Ti and Co are being used in this application due to the low resistivity of TiSi 2 and of CoSi 2 . 4,5 Ti silicide is currently widely used by industry, but scaling it to deep-submicrometer features is difficult for transformation from the C49 to the C54 phase so that the resistance of TiSi 2 is higher at a narrow linewidth and agglomeration of TiSi 2 is easier at small dimensions. The latter effect can be suppressed by decreasing subsequent thermal budgets after formation of Ti silicide. Co silicide has been a strong candidate because of no linewidth dependence of silicide sheet resistance down to 0.065 m and because of thermal stability higher than Ti silicide. However, it has disadvantages such as diode leakage and sensitivity to the surface cleanness before metal deposition. Solutions to solve diode leakage are a short time Ar/H 2 sputter clean by etching, a premetal deposition amorphization implantation prior to Co deposition, high-temperature silicide formation ͑silicidation͒, and high-temperature metal deposition. 6 In order to achieve surface cleanliness, the Ti cap process makes the silicidation process less sensitive to the presence of the native oxide or to O-rich ambient contaminants in the rapid thermal processing system. 7 Co silicide does not have any properti...

show abstract

supporting

confidence: 77%

The Effects of Residual RTOs on Formation of CoSi[sub 2] and Its Properties for 0.18 μm CMOS

Lee

2004

J. Electrochem. Soc.

View full text Add to dashboard Cite

show abstract

“…Then 10 nm Co or 12 nm Ni was deposited and the deposited metal thickness was carefully calibrated by cross-sectional TEM. For Co germano-silicide, the first step silicidation was performed at 500 C for 30 s and the second phase transformation was excused at 750 to 1000 C by RTA [9]- [12]. For Ni germano-silicide, only one-step RTA at 350-700 C for 30 s was performed.…”

Section: Methodsmentioning

confidence: 99%

“…Using the high temperature stable SiGe formed by solid-phase epitaxy, ultrathin gate oxide grown on SiGe can achieve comparable integrity with that on Si and the same time achieving 2 times hole mobility improvement [1]- [3]. However, to integrate SiGe p-MOSFET into current VLSI process, high quality silicide [9]- [12] on SiGe is unavoidable. Unfortunately, little study of germano-silicide on single crystalline SiGe can be found in the literature, which may be due to the strong agglomeration [8] at high temperatures.…”

Section: Introductionmentioning

confidence: 96%

Formation of Ni germano-silicide on single crystalline Si/sub 0.3/Ge/sub 0.7//Si

Lin

Chen²,

Lai

et al. 2002

IEEE Electron Device Lett.

View full text Add to dashboard Cite

We have studied the Ni and Co germano-silicide on Si 0 3 Ge 0 7 Si. The Ni germano-silicide shows a low sheet resistance of 4-6 on both P + N and N + P junctions, which is much smaller than Co germano-silicide. In addition, small junction leakage currents of 3 10 8 A cm 2 and 2 10 7 A cm 2 are obtained for Ni germano-silicide on P + N and N + P junctions, respectively. The good germano-silicide integrity is due to the relatively uniform thickness as observed by cross-sectional TEM.

show abstract

“…While care must be taken to maintain electrical isolation between the epitaxy and the polysilicon, this T-shaped gate structure is key to reducing the narrow linewidth effect for self-aligned silicide (salicide) processes. 43 Note that the polysilicon linewidth quoted in this discussion refers to the original width before selective silicon deposition.…”

Section: Facet Formation and Suppression-tablementioning

confidence: 99%

Facet‐Free Selective Silicon Epitaxy by Reduced‐Pressure Chemical Vapor Deposition Process Evaluation and Impact on Shallow Trench Isolation

Violette

Chao

Wise

et al. 1999

J. Electrochem. Soc.

View full text Add to dashboard Cite

A facet-free, selective epitaxy process has been identified using the SiH 2 Cl 2 /HCl/H 2 chemistry in single-wafer reduced-pressure chemical vapor deposition. The process window has been explored with respect to shallow trench isolation, simultaneous polycrystalline silicon (polysilicon) deposition, facet formation, and electrical parameters of polysilicon sheet resistance and junction leakage current. The isolation structure can be severely degraded by aggressive pre-epitaxy bakes through volatile SiO formation; however, the impact is minimized when the prebake is limited to 900ЊC, 60 s. Concurrent deposition of polysilicon and silicon epitaxy can result in significantly different deposition rates. Low process pressures result in greater relative epitaxy growth rates and high pressures result in lower relative epitaxy deposition rates. The facet-free process depends heavily on both the gate sidewall structure and the process conditions, where the combination of an undercut into the pad oxide and the nitride sidewall with the process pressure yield a reliably facet-free process. Electrical results demonstrate that standard Ti or Co self-aligned silicidation can be extended into a 0.1 m gate length regime.

show abstract

Low resistance Ti or Co salicided raised source/drain transistors for sub-0.13 μm CMOS technologies

Cited by 17 publications

References 2 publications

The Effects of Residual RTOs on Formation of CoSi[sub 2] and Its Properties for 0.18 μm CMOS

The Effects of Residual RTOs on Formation of CoSi[sub 2] and Its Properties for 0.18 μm CMOS

Formation of Ni germano-silicide on single crystalline Si/sub 0.3/Ge/sub 0.7//Si

Facet‐Free Selective Silicon Epitaxy by Reduced‐Pressure Chemical Vapor Deposition Process Evaluation and Impact on Shallow Trench Isolation

Contact Info

Product

Resources

About