Low-Overhead, High-Speed Multi-core Barrier Synchronization

Sartori, John; Kumar, Ravi

doi:10.1007/978-3-642-11515-8_4

Cited by 25 publications

(7 citation statements)

References 13 publications

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“…However, one primary drawback of such approach is the performance overhead related to the hardware configuration (e.g., DMA programming) and interrupt handling (e.g., DMA transfer completion interrupt, lock available interrupt). In the context of MPSoC, these overheads are not negligible, since finegrained parallelisms can be highly sensitive to communication latency [2], [6]. Moreover, using separated hardware blocks, respectively for message-passing and synchronization, also results in area and power overhead, especially for resource-constrained embedded systems.…”

Section: Introductionmentioning

confidence: 99%

Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology

Xiao

Isshiki

et al. 2012

IPSJ Transactions on System LSI Design Methodology

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Inter-processor communication and synchronization are critical problems in embedded multiprocessors. In order to achieve high-speed communication and low-latency synchronization, most recent designs employ dedicated hardware engines to support these communication protocols individually, which is complex, inflexible, and error prone. Thus, this paper motivates the optimization of inter-processor communication and synchronization by using application-specific instruction-set processor (ASIP) techniques. The proposed communication mechanism is based on a set of custom instructions coupled with a low-latency on-chip network, which provides efficient support for both data transfer and process synchronization. By using state-of-the-art ASIP design methodology, we embed the communication functionalities into a base processor, making the proposed mechanism feature ultra low overhead. More importantly, industry-standard compatible programming interfaces supporting both message-passing and shared-memory paradigms are exposed to end-users to ease the software porting. Experimental results show that the bandwidth of the proposed message-passing protocol can achieve up to 703 Mbyte/s @ 200 MHz, and the latency of the proposed synchronization protocol can be reduced by more than 81% when compared with the conventional approach. Moreover, as a case study, we also show the effectiveness of the proposed communication mechanism in a real-life embedded application, WiMedia UWB MAC.

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Section: Introductionmentioning

confidence: 99%

Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology

Xiao

Isshiki

et al. 2012

IPSJ Transactions on System LSI Design Methodology

View full text Add to dashboard Buy / Rent full text

show abstract

“…NAS Parallel Benchmarks. We chose the CG and MG kernels from the C versions [15] of the NAS Parallel Benchmarks (NASPB) [1] in order to evaluate the efficiency of barrier synchronization [5,14,16]. As the original inputs for these benchmarks lead to a low frequency of barrier synchronization, even using the smallest class S, which makes it difficult to observe barrier overhead, we introduced our own input class Y for these 2 NASPB kernels.…”

Section: Benchmarksmentioning

confidence: 99%

Effective Barrier Synchronization on Intel Xeon Phi Coprocessor

Rodchenko

Nisbet

Pop

et al. 2015

Lecture Notes in Computer Science

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Abstract. Barriers are a fundamental synchronization primitive, underpinning the parallel execution models of many modern shared-memory parallel programming languages such as OpenMP, OpenCL or Cilk, and are one of the main challenges to scaling. State-of-the-art barrier synchronization algorithms differ in tradeoffs between critical path length, communication traffic patterns and memory footprint. In this paper, we evaluate the efficiency of five such algorithms on the Intel Xeon Phi coprocessor. In addition, we present a novel hybrid barrier implementation that exploits the Xeon Phi's topology, memory hierarchy and streaming stores to achieve a 3× lower overhead than the Intel OpenMP barrier implementation (ICC 14.0.0), thus outperforming, to the best of our knowledge, all other implementations, and which we evaluate on the CG and MG kernels from the NAS Parallel Benchmarks, the direct N-body simulation kernel and the EPCC barrier OpenMP microbenchmark.

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“…Many efficient designs and algorithms have been proposed for on-chip multi-processor systems [10,11]. In the area of large-scale multi-processors various approaches have been taken to support global operations.…”

Section: Related Workmentioning

confidence: 99%

AWGR-Based Optical Topologies for Scalable and Efficient Global Communications in Large-Scale Multi-Processor Systems

Yoo

Akella

2012

J. Opt. Commun. Netw.

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In large-scale multi-processor computing systems, global communications are typically supported by an auxiliary network (e.g., IBM Blue Gene) or with hardware support in the network (e.g., NEC Earth Simulator). We explore the potential for realizing efficient global communications that can scale beyond a million processors by harnessing the unique parallelism and wavelength routing properties of optical devices. Specifically, we use an arrayed waveguide grating router (AWGR) device as the basic building block in realizing scalable global communication. The AWGR is a passive switch fabric (wavelength router) that uses multiple wavelengths to interconnect outputs and inputs by following a specific cyclic wavelength routing (permutation) pattern. We analyze different network topologies using AWGR devices for barrier synchronization and propose techniques to pick parameters of the network for a given number of processors. We compare the performance and energy consumption for barrier synchronization with what is achievable with state-of-the-art electrical networks.

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Low-Overhead, High-Speed Multi-core Barrier Synchronization

Cited by 25 publications

References 13 publications

Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology

Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology

Effective Barrier Synchronization on Intel Xeon Phi Coprocessor

AWGR-Based Optical Topologies for Scalable and Efficient Global Communications in Large-Scale Multi-Processor Systems

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