Low Leakage Fully Half-Select-Free Robust SRAM Cells With BTI Reliability Analysis

Ahmad, Sayeed; Iqbal, Belal; Alam, Naushad; Hasan, Mohd.

doi:10.1109/tdmr.2018.2839612

Cited by 61 publications

(49 citation statements)

References 32 publications

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“…Hence, probability of read failure incident is extremely increased. On the other hand, with severe V DD scaling, write operation of C6T fails, and as a result, intended data are not written at the storage nodes because it is unable to keep the devices strength ratio in such a V DD 6 . Furthermore, C6T is very sensitive to the process, voltage, and temperature (PVT) variations, and hence, its RSNM and write static noise margin (WSNM), as a measure of its write ability, degrade quickly 7 …”

Section: Introductionmentioning

confidence: 99%

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Abbasian

Gholipour

2021

Circuit Theory & Apps

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Summary This paper presents an 11 transistor (SEHF11T) static random access memory (SRAM) cell with high read static noise margin (RSNM) and write static noise margin (WSNM). It eliminates the write half‐select disturb using cross‐point data‐aware write word lines, which can mitigate bit‐interleaving structure to reduce multiple‐bit upset and increase soft‐error immunity. We evaluated and analyzed the effect of process, voltage, and temperature (PVT) variations on various design metrics and compared it with other cells. The SEHF11T performs fast read operation due to its higher read current and slow write operation due to its single‐ended nature. It employs the read decoupling technique to enhance the RSNM. The stacked transistors in the left/right half‐cell increase the RSNM. In addition, the WSNM is improved by eliminating the feedback of cross‐coupled inverters pair during write operation by means of power‐cutoff write‐assist technique. The proposed cell shows 1.11X higher RSNM and 1.37X higher WSNM compared to fully differential 8T (FD8T) cell. The stacked transistors in the cell reduce leakage power dissipation. The SEHF11T consumes 0.47X lower leakage power compared to FD8T at VDD = 0.7 V. Furthermore, it exhibits high reliability against PVT variations in subthreshold region and shows 1.09X narrower spread in leakage power than that of FD8T at VDD = 0.3 V.

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Section: Introductionmentioning

confidence: 99%

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Abbasian

Gholipour

2021

Circuit Theory & Apps

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“…Factors, which affect the read and write stability of an SRAM cell are carefully considered in this design. Normally, the

β

ratio should lie between 1.2 and 3 for good RSNM (read static noise margin) [27]. Typically,

γ

ratio ≤1.2 should be good for WSNM (write static noise margin).…”

Section: Simulation Resultsmentioning

confidence: 99%

Single bit‐line 11T SRAM cell for low power and improved stability

Lorenzo

Pailly

2020

IET Computers & Digital Techniques

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This study aims for a new 11T static random access memory (SRAM) cell that uses power gating transistors and transmission gate for low leakage and reliable write operation. The proposed cell has a separate read and write path which successfully improves read and write abilities. Furthermore, it solves the row half select disturbance and utilises a row-based virtual ground signal to eliminate unnecessary bit-line discharge in the un-selected row, thus decreasing energy consumption. The cell also achieves low power due to the stack effect. To show the effectiveness of the cell, its design metrics are compared with other published SRAM cells, namely, conventional 6T, 10T, 9T, and power-gated 9T (PG9T). In standby mode, from 6.71 to 7.37% leakage power reduction is observed for this cell at an operating voltage of 1.2 V and 29.21 to 58.68% & 32.74 to 71.11% improvement for write & read power over other cells. The proposed cell exhibits higher write and reads static noise margins with an improvement of 13.54 and 63.28%, respectively, compared to conventional 6T SRAM cell. The cell provides write delay improvement from 29.77 to 49.40% and read delay improvement from 7 to 12% compared to 9T, 10T, and PG9T, respectively.

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“…To implement in a BI architecture and consequence solving multi-bit errors, an SRAM cell must be HS-disturb-free. 35 Since the proposed SE12T cell utilizes a read buffer; formed by two serially access NMOS transistor, to isolate the bitline from the storage nodes, there will be no disturbance during the read operation. Therefore, in this subsection, we discussed and proved that the proposed SE12T cell is fully HS-disturb-free during the write operation.…”

Section: Elimination Of Half-select Disturbance Problemsmentioning

confidence: 99%

Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design

Abbasian

Gholipour

Izadinasab

2021

Circuit Theory & Apps

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Graphene nanoribbon and transition metal dichalcogenide field-effect transistors (GNRFETs and TMDFETs) have emerged as favorable candidates to replace conventional metal-oxide-semiconductor (MOS) transistor in future technologies. Their competence must be proven through the study and evaluation of various circuits, including static random access memories (SRAMs). Therefore, this paper presents a single-ended 12T (SE12T) SRAM cell designed using GNRFETs and TMDFETs to evaluate their performance. The proposed SE12T cell designed with GNRFETs/TMDFET device improves read static noise margin by 1.95Â/3.20Â and incurs a penalty of 1.16Â/1.14Â in read delay compared to the GNRFETs/TMDFET-based fully differential 8T cell through a read buffer, decoupling the bitline from the storing nodes during the read operation. Furthermore, two transmission gates (TGs) placed inside the cell core cut off the feedback of cross-coupled inverters pair during the write operation, enhancing write static noise margin by 1.65Â/1.71Â. These two TGs along with high logic level of virtual ground (V GND ) control signal during hold mode reduce leakage power. Existence of a higher number of p-type MOS (PMOS) devices, the presence of stacked transistors, and being single-ended bitcell further reduce this metric, nearly 1.48Â/1.17Â designed with GNRFETs/TMDFET device as compared to FD8T. Furthermore, it is observed from the results that GNRFET-based designs have better performance than those of their TMDFET counterparts. The proposed cell eliminates write half-select disturb, and therefore, bit-interleaving architecture can be applied to reduce multi-bit errors.

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Low Leakage Fully Half-Select-Free Robust SRAM Cells With BTI Reliability Analysis

Cited by 61 publications

References 32 publications

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Single bit‐line 11T SRAM cell for low power and improved stability

Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design

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