2015
DOI: 10.1109/tmtt.2015.2479233
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Low-Input Power-Level CMOS RF Energy-Harvesting Front End

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Cited by 43 publications
(15 citation statements)
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“…Generally, off-chip inductors have larger Q-factor compared to on-chip inductors. As an example, with an off-chip inductor with a Q-factor that is four times higher compared to an on-chip inductor, the voltage gain is increased by a factor of two in comparison to its on-chip counterpart [37]. Hence, the Q-factor of the IMN inductor plays a significant role in enhancing the sensitivity performance of the RFEH system by boosting VAnt to drive the transistors of the rectifier in improving the operation.…”
Section: B Impedance Matching Network (Imn)mentioning
confidence: 99%
See 1 more Smart Citation
“…Generally, off-chip inductors have larger Q-factor compared to on-chip inductors. As an example, with an off-chip inductor with a Q-factor that is four times higher compared to an on-chip inductor, the voltage gain is increased by a factor of two in comparison to its on-chip counterpart [37]. Hence, the Q-factor of the IMN inductor plays a significant role in enhancing the sensitivity performance of the RFEH system by boosting VAnt to drive the transistors of the rectifier in improving the operation.…”
Section: B Impedance Matching Network (Imn)mentioning
confidence: 99%
“…The Q factor of an on-chip inductor is dependant on parasitics which is proportional to the technology node [38]. Nevertheless, there are various techniques reported in improving the Q-factor through the physical design innovation of on-chip inductors [37,39,40] and high-Q co-design antenna [10,41] to attain superior performance in sensitivity. Table I summarizes the Q-factor of various inductors.…”
Section: B Impedance Matching Network (Imn)mentioning
confidence: 99%
“… indicates that a sensitivity of up to −40 dBm at 2.45 GHz can be achieved by using tunnel diodes. Furthermore, three stages of voltage doubler designed in 0.18 µm CMOS technology with a matching network have demonstrated to achieve 1 V output voltage at −27 dBm input power . However, in CMOS technology, there are certain undesirable parasitic effects that degrade the performances.…”
Section: Introductionmentioning
confidence: 99%
“…Furthermore, three stages of voltage doubler designed in 0.18 mm CMOS technology with a matching network have demonstrated to achieve 1 V output voltage at 227 dBm input power. 4 However, in CMOS technology, there are certain undesirable parasitic effects that degrade the performances. These parasitic effects are reduced in the FDSOI technology.…”
Section: Introductionmentioning
confidence: 99%
“…The idea is to make the devices to harvest the available surrounding power and transfer to the electrical power which can be stored in the battery. There are a lot of power energy sources lies around us such as radio frequency (RF), vibration, solar, wind and thermal [1][2][3][4][5]. Up to date, the present energy harvesting only generates small electrical power, which depends on technique and concept used in the system.…”
Section: Introductionmentioning
confidence: 99%