Local NOR and global NAND match-line architecture for high performance CAM

Ahn, Sung-Gi; Kwon, Kee-Won

doi:10.1109/mwscas.2017.8053021

Cited by 10 publications

(6 citation statements)

References 5 publications

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“…Since the proposed design forms a CAM word with 2 ML partitions (NAND & NOR), we focus on works with segmentation schemes [13][14][15]27] and hybrid MLs [16-19, 22, 28]. In SMA-CAM [13], a match-line row is segmented into two sets of precharge section and charge-shared section.…”

Section: Related Workmentioning

confidence: 99%

“…Current limiting and clamping scheme saturates the voltage of multiple local ML segments to certain levels and, consequently limits the amount of discharging to save ML dynamic power [14]. Unlike in SMA [13] and local-global ML architecture [14], where ML is segmented into various sections, ML division and controlled CAM (MLDC-CAM) [15] divide a high-speed NOR-ML into only two sections. Both the ML sections operate simultaneously so that delay is close to that of the high-speed conventional CAM.…”

Section: Related Workmentioning

confidence: 99%

“…Because only a subset of MLs is precharged, peak power and average power is saved conditionally. Current limiting and clamping scheme saturates the voltage of multiple local ML segments to certain levels and, consequently limits the amount of discharging to save ML dynamic power [14]. Unlike in SMA [13] and local-global ML architecture [14], where ML is segmented into various sections, ML division and controlled CAM (MLDC-CAM) [15] divide a high-speed NOR-ML into only two sections.…”

Section: Related Workmentioning

confidence: 99%

“…NOR match-line is segmented into several precharge and charge-shared MLs in segmented ML architecture (SMA) [13] for reducing the average power during the search. Another variant of NOR-ML is split into high-speed local segments and assembled into a lighter global ML generator for reducing the dynamic power of the segments [14]. Dividing a high-speed NOR-ML into dual-section controls needless discharges of the second yet dominant ML section to reduce power dissipation of CAM [15].…”

Section: Introductionmentioning

confidence: 99%

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Match‐line control unit for power and delay reduction in hybrid CAM

Hussain

Mahendra²,

Mishra

et al. 2021

IET Circuits, Devices & Syst

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Content addressable memory (CAM) is a hardware search engine utilised for accelerating translation and table look‐up in network routers and data processing systems. This article proposes a NAND‐NOR match‐line (ML) based CAM architecture with the main goals of elevating search performance and energy efficiency. A competent ML control unit (MLCU) is introduced to provide a short discharge path for output match‐line after processing the ML sections. In this architecture, tag mismatch based on memory traces is utilised (in NAND‐MLs) to deactivate redundant NOR‐MLs in an attempt to reduce the overall ML switching activity. Based on the decision of NAND‐ML partition, the MLCU restores the charge to reduce ML glitches during the evaluation phase. Match‐line delay of the proposed 64×32‐bit hybrid CAM is 366.90 ps in a standard 45‐nm technology at 1 V, which is 56.51% and 72.55% reductions compared to a conventional CAM and a segmented CAM, respectively. Reduction in precharge power and search power of the presented CAM leads to 6× enhancements of power‐delay‐product from existing hybrid CAMs. The proposed CAM can operate up to low supply voltages by dissipating only 0.10 fJ/bit/search at 0.5 V.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Match‐line control unit for power and delay reduction in hybrid CAM

Hussain

Mahendra²,

Mishra

et al. 2021

IET Circuits, Devices & Syst

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show abstract

“…In the prevalent NOR-type TCAM, all MLs are pre-charged and most of them are discharged in each comparison cycle. Consequently, MLs contribute the most to power consumption, with the toggling of SLs following MLs in terms of power consumption [5,6].…”

Section: Introductionmentioning

confidence: 99%

Dynamic Power Reduction in TCAM Using Advanced Selective Pre-Charging of Match Lines

Doo,

Kwon

2023

Electronics

Self Cite

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In this paper, we propose a power-efficient memory operation, selective match line precharge, based on an analysis of power consumption in ternary content-addressable memory (TCAM). A statistical study reveals that, on average, 58% of power dissipation related to the match line operation is saved by deactivating the unnecessary swing of match lines. The improvement has been simulated and proved using 180 nm CMOS technology.

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Design and Implementation of Reversible Logic Based Ternary Content Addressable Memory

Santhi

Babu

2019

Smart Intelligent Computing and Applications

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Local NOR and global NAND match-line architecture for high performance CAM

Cited by 10 publications

References 5 publications

Match‐line control unit for power and delay reduction in hybrid CAM

Match‐line control unit for power and delay reduction in hybrid CAM

Dynamic Power Reduction in TCAM Using Advanced Selective Pre-Charging of Match Lines

Design and Implementation of Reversible Logic Based Ternary Content Addressable Memory

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