Lithography manufacturing implementation for 65 nm and 45 nm nodes with model-based scattering bars using IML technology

Hsu, Michael; Broeke, Doug Van Den; Laidig, Tom; Wampler, Kurt E.; Hollerbach, Uwe; Socha, Robert; Chen, J. F.; Hsu, Stephen; Shi, Xuelong

doi:10.1117/12.598589

Cited by 1 publication

(3 citation statements)

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“…A possible scenario is to first simultaneously optimize the source and the mask [8] on the cell of a memory device or on critical patterns of a logic device. Then using the optimized source for the cell or critical pattern apply IML to the rest of the device (the periphery for a memory device or the non-critical patterns for a logic device).…”

Section: Discussionmentioning

confidence: 99%

“…Consequently, a technique for placing the scatter bars is needed when using the source optimized for the critical pattern. This technique is interference mapping lithography (IML) in which the scatter bars are placed in the optimal location through a model 6,7,8 . In interference mapping, the inference map is calculated for the remaining non-critical areas.…”

Section: Smo and Iml For Full Chip Source Mask Optimizationmentioning

confidence: 99%

“…After calculating the first eigenfunction φ'(x,y), the interference map is calculated by convolving the pattern with first eigenfunction as described in references [6,7,8] . The assist features are then placed in areas of the interference map that cause best interference.…”

Section: U a T I O N 1 5 The Quantity Inside The Brackets [ ] In Eqmentioning

confidence: 99%

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Simultaneous source mask optimization (SMO)

Socha¹,

Shi²,

LeHoty³

2005

SPIE Proceedings

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In this paper, a method for improving the process window is described by simultaneous source mask optimization (SMO). The method optimizes the source and mask of a critical pattern by optimizing the mask in the frequency domain. The minimum image log slope (ILS) is maximized at fragmentation points in the critical pattern while simultaneously maintaining the printing fidelity. The mask optimized in the frequency domain is then converted into a chromeless phase lithography (CPL) mask. The process window with the optimized source and optimized CPL mask doubles the aerial image contrast in comparison to an attenuating PSM with source optimization only. After optimizing the mask and source for a critical pattern, the remaining parts of the full-chip design are optimized with interference mapping. Another technique for optimizing the source for a full chip is presented in which the source is optimized by using the pitch frequency of the design. From the pitch frequency, the source is optimized by solving an integral equation for the first eigenfunction in which the first eigenfunction is calculated from the sum of coherent system (SOCS) representation of the transfer cross coefficient (TCC).

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Section: Discussionmentioning

confidence: 99%

Section: Smo and Iml For Full Chip Source Mask Optimizationmentioning

confidence: 99%