Limitation of WSix/WN Diffusion Barrier for Tungsten Dual Polymetal Gate Memory Devices

Lim, Kwan-Yong; Sung, Min-Gyu; Kim, Y.S.; Cho, H.-J.; Lee, S.-R.; Jang, Se-Aug; Choi, Soo-Han; Lee, Y.-J.; Oh, Taekyung; Chun, Yunseok; Kim, Y.-H.; Choi, K.S.; Kim, K.O.; Jung, Young-Kyun; Koo, Sang-Sool; Ma, Wenjie; Han, Jin−Woo; Kim, G.-H.; Kim, S.-J.; Won, S.-R.; Shin, Seung-woo; Lee, J.-K.; Youn, Tae-Un; Kim, W.; Hwang, Yun-Taek; Yang, Heesu; Pyi, Seung-Ho; Kim, J.-W.

doi:10.1109/relphy.2007.369975

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“…1) and abnormal high gate oxide leakage current of in pMOS at several sites [ Fig. 2], Ti/WN diffusion barrier is more suitable for the W-DPG application [1][2][3]. However, the tungsten film deposited on Ti/WN barrier shows not only more than twice higher electrical resistivity than WSix/WN barrier but also abnormally high gate sheet resistance (Rs) due to a narrow line width effect.…”

Section: Introductionmentioning

confidence: 99%

Low resistive tungsten dual polymetal gate process for high speed and high density memory devices

Kim

Lim

Sung

et al. 2007

ESSDERC 2007 - 37th European Solid State Device Research Conference

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We developed ultra-low resistive tungsten dual polymetal gate memory device by using Ti-based diffusion barrier and a unique tungsten chemical vapor deposition (CVD) process with B 2 H 6 -based nucleation layer. The low resistive CVD-W (LRW) polymetal gate process not only reveals good gate oxide reliability comparable to PVD-W process, but also highly improved transistor performances such as signal delay characteristics.

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Section: Introductionmentioning

confidence: 99%