Leakage current and reliability evaluation of ultra-thin reoxidized nitride and comparison with silicon dioxides

An experimental study has been carried out to estimate the heat transfer improvement offered by a novel electro-osmotic (EO) heat spreader for microprocessor cooling. The proposed design of the elliptical silicon heat spreader can be fabricated at the back surface of the microprocessor as an integral part. Thus, no extra space may be required. The EO heat spreader developed is 0.6 mm 3 in volume and it contains a pair of thin gold film electrodes of approximately 1 lm thickness for applying an external electric field that induces electro-osmotic flow. The inner channel surfaces of the heat spreader are electrically insulated with a thin SiO 2 layer to minimize current leakage into the wafer. The EO heat spreader constructed is able to generate a flow rate of 0.2028 ll/min at 2 V/mm. With this heat spreader, the temperature of a heat source may be reduced by up to 4°C without the aid of any external mechanical devices. The heat spreader has the potential to make the temperature uniform, if the heat source is non-uniform in nature.

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“…5) of less than 1 mV. This value is inline with the zeta potential measured in references (Wu et al 2002;Chen and Singh 2003).…”

Section: Flow Measurement Resultssupporting

confidence: 89%

“…This is because, silicon dioxide surface gives a higher zeta potential of 12.20 mV than pure silicon. This value also falls into the range of measured value reported (Wu et al 2002;Chen and Singh 2003). Therefore, it has been used as the EO micro-pump in the proposed heat spreader.…”

Section: Flow Measurement Resultssupporting

confidence: 56%

An experimental study on an electro-osmotic flow-based silicon heat spreader

Eng

Nithiarasu

Guy

2010

Microfluid Nanofluid

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“…At the same time the industry was moving to MG to eliminate the poly depletion problem, it also had to address the problem of tunneling leakage through the gate dielectric. In early 2000's, the conventional Silicon Oxynitrides (SiON) dielectric at ~1.2-1.7nm thickness [Intel at ~1.2nm 26 and IBM at ~1.7nm 27 ] was leaking up to 30% of the channel current. The transition from SiO 2 (k~3.9) to SiON (k~4.5) in the 130nm node and then to HfO 2 (k~20) at the 45nm node provided similar or even improved capacitances at gate dielectric thicknesses large enough to essentially eliminate the leakage problem 28,26 .…”

Section: Channel and Gate Engineeringmentioning

confidence: 99%

Scaling Challenges for Advanced CMOS Devices

Jacob

Xie

Sung

et al. 2017

Int. J. Hi. Spe. Ele. Syst.

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The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore's law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

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“…While this yields a very-high-quality film in terms of low leakage current and high breakdown voltage, it is only so for film thicknesses above 200 nm. [10] Hereafter in this article, the SiN x deposited by the aforementioned gas mixture will be referred to as conventional SiN x .…”

mentioning

confidence: 99%

Vertical Transistor with Ultrathin Silicon Nitride Gate Dielectric

et al. 2009

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Nanoscale vertical thin‐film transistors (VTFTs) are fabricated employing a new ultrathin silicon nitride (SiNx) gate dielectric for applications in high‐resolution active matrix flat panel electronics. Illustrated are the cross‐section schematic and SEM image of a 500 nm channel length VTFT with a 50 nm thick SiNx gate dielectric. The device demonstrates excellent gate control with gate leakage as low as 0.1 nA cm−2.

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Leakage current and reliability evaluation of ultra-thin reoxidized nitride and comparison with silicon dioxides

Cited by 5 publications

References 46 publications

An experimental study on an electro-osmotic flow-based silicon heat spreader

An experimental study on an electro-osmotic flow-based silicon heat spreader

Scaling Challenges for Advanced CMOS Devices

Vertical Transistor with Ultrathin Silicon Nitride Gate Dielectric

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