LEAF: A System Level Leakage-Aware Floorplanner for SoCs

Gupta, Aseem; Dutt, Nikil; Kurdahi, Fadi; Khouri, K.S.; Abadir, Magdy S.

doi:10.1109/aspdac.2007.357998

Cited by 19 publications

(8 citation statements)

References 12 publications

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“…As temperature increases, the leakage power dissipation increases which further elevates the temperature. This 'positive feedback loop' between temperature and leakage power stabilizes when steady state operating temperatures have been reached at which state, all the dynamic and leakage power dissipation is transferred to the environment by the package [4]. This discussion implies that probability of error is not a monotonically decreasing function of supply voltage but rather exhibits a convex behavior as shown in Fig.…”

Section: A Sources Of Errorsmentioning

confidence: 97%

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TRAM: A tool for Temperature and Reliability Aware Memory Design

Khajeh

Gupta

Dutt

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large percentage of the total system's power dissipation, area and reliability. In this paper, we present a tool which captures the effects of supply voltage V dd and temperature on memory performance and their interrelationships. We propose a Temperature-and Reliability-Aware Memory Design (TRAM) approach which allows designers to examine the effects of frequency, supply voltage, power dissipation, and temperature on reliability in a mutually interrelated manner. Our experimental results indicate that thermal unaware estimation of probability of error can be off by at least two orders of magnitude and up to five orders of magnitude from the realistic, temperature-aware cases. We also observed that thermal aware V dd selection using TRAM can reduce the total power dissipation by up to 2.5X while attaining an identical predefined limit on errors.

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Section: A Sources Of Errorsmentioning

confidence: 97%

“…Finally, temperature has a very significant impact on the leakage power dissipation. In fact, there exists a positive feedback loop between temperature and leakage power [4].…”

Section: Introductionmentioning

confidence: 99%

TRAM: A tool for Temperature and Reliability Aware Memory Design

Khajeh

Gupta

Dutt

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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“…All the current thermal-aware floorplanners consider only a single leader power profile found by computing the average power values [2] [4] (referred to as average-leader floorplanner) or peak power values…”

Section: B Comparison With Peak and Average Power Leadersmentioning

confidence: 99%

“…The physical layout of blocks (floorplan) plays a significant role on thermal behavior of the chip. Hence, many existing work on thermal estimation and analysis is on a given layout or toward generating a thermal-aware layout (Thermalaware Floorplanning) [2]- [4] However, all recently developed thermal-aware tools deploy temperature estimation techniques only on a single power profile representing power profiles of all inputs and all applications (e.g. using average or peak power profile).…”

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confidence: 99%

Statistical power profile correlation for realistic thermal estimation

Singhal

Bozorgzadeh

2008

2008 Asia and South Pacific Design Automation Conference

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Abstract-At system level, the on-chip temperature depends both on power density and the thermal coupling with the neighboring regions. The problem of finding the right set of input power profile(s) for accurate temperature estimation has not been studied. Considering only average or peak power density may lead either to underestimation or overestimation of the thermal crisis, respectively. To provide more realistic temperature estimation, we propose to incorporate multiple power profiles. Using the proposed statistical methods to determine the closeness between the power profiles, we apply a clustering algorithm to identify few input power profiles. We incorporate them in a thermal-aware floorplanner and empirical results show that using the single input power profile (average or peak) leads to 37% degradation in critical wire delay and 20% degradation in wire length, compared to using the multiple input power profiles.

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“…Second, it presents design and architectural solutions that reduce the thermal variation of caches, enhancing the lifetime reliability of the caches and making them appear closer to what is typically modeled, and enhancing their ability to absorb heat from neighboring structures without adverse effects. Third, it presents architectural solutions to reduce the steady-state temperature of the cache, by reducing the temperature of the hotspot peripherals within the cache -this results in significant reduction of cache leakage power (due to interdependence of leakage and temperature [30]) and reduction of SRAM cache failure probability [29].…”

Section: Introductionmentioning

confidence: 99%

Hot peripheral thermal management to mitigate cache temperature variation

Homayoun

Rahmatian

Kontorinis

et al. 2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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Abstract-Modern microprocessor caches are often regarded as cool chip components that dissipate power uniformly. This research demonstrates that this uniformity is a misconception. Memory cell peripherals dissipates considerably higher power than the actual memory cell and this can result in up to 30 o C of temperature difference between the warmest and the coolest cache part. To be effective and accurate, cache temperature and power modeling and management must take this effect into account. We focus on the surrounding logic of the memory cell and apply two novel techniques, peripheral bit swapping (PBS) and peripheral monitor and shutdown (PMSD), to reduce the thermal variation and reduce the corresponding steady-state temperature and leakage power of the cache. Overall, our techniques, on average, decrease temperature by 8 o C for the L1 Data Cache and 5 o C for the shared L2 cache and reduce their thermal gradient by more than 75%, on average, and across SPEC2K benchmarks.I.

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LEAF: A System Level Leakage-Aware Floorplanner for SoCs

Cited by 19 publications

References 12 publications

TRAM: A tool for Temperature and Reliability Aware Memory Design

TRAM: A tool for Temperature and Reliability Aware Memory Design

Statistical power profile correlation for realistic thermal estimation

Hot peripheral thermal management to mitigate cache temperature variation

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